Patents by Inventor Yoshio Hayashide

Yoshio Hayashide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705272
    Abstract: A coil component includes: a coil embedded in a substrate body and having a winding part constituted by a wound conductor; wherein the substrate body has: a first region sandwiched between one end surface of the substrate body and a plane parallel with the one end surface and running through a portion of a first external electrode farthest away from the one end surface; a second region sandwiched between another end of the substrate body and a plane parallel with the another end surface and running through a portion of a second external electrode farthest away from the another end surface; and a third region between the first region and the second region; and the winding part is provided in the third region, and also in the first region where it is wound by one turn or more.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 18, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenichiro Nogi, Yoshio Hayashide
  • Publication number: 20200105462
    Abstract: A coil component includes: a coil embedded in a substrate body and having a winding part constituted by a wound conductor; wherein the substrate body has: a first region sandwiched between one end surface of the substrate body and a plane parallel with the one end surface and running through a portion of a first external electrode farthest away from the one end surface; a second region sandwiched between another end of the substrate body and a plane parallel with the another end surface and running through a portion of a second external electrode farthest away from the another end surface; and a third region between the first region and the second region; and the winding part is provided in the third region, and also in the first region where it is wound by one turn or more.
    Type: Application
    Filed: September 13, 2019
    Publication date: April 2, 2020
    Inventors: Kenichiro NOGI, Yoshio HAYASHIDE
  • Patent number: 7465221
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 7465216
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Publication number: 20070270086
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 22, 2007
    Applicant: RENESAS TECHNOLOGY CORP
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Publication number: 20070264908
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 7258598
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: August 21, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 6914011
    Abstract: A film deposition system comprises a chamber having an internal space, a support part provided in the internal space of the chamber for supporting a substrate, a gas supply part supplying gas to the internal space and a heating part heating the substrate. After an oxide film is formed on the substrate, the gas supply part supplies oxygen or a gas mixture of oxygen and ozone to the internal space while the heating part heats the substrate. Thus provided is a film deposition system capable of flattening an oxide film.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: July 5, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshio Hayashide, Kazuo Kobayashi, Yasufumi Morimoto
  • Publication number: 20040163599
    Abstract: A film deposition system comprises a chamber having an internal space, a support part provided in the internal space of the chamber for supporting a substrate, a gas supply part supplying gas to the internal space and a heating part heating the substrate. After an oxide film is formed on the substrate, the gas supply part supplies oxygen or a gas mixture of oxygen and ozone to the internal space while the heating part heats the substrate. Thus provided is a film deposition system capable of flattening an oxide film.
    Type: Application
    Filed: August 14, 2003
    Publication date: August 26, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yoshio Hayashide, Kazuo Kobayashi, Yasufumi Morimoto
  • Publication number: 20040016987
    Abstract: It is possible to obtain a semiconductor device with an element isolation structure showing a good isolation characteristic by filing an interior of a minute trench with a good quality insulating film free of a defect such as a void, and a manufacturing method therefor. The semiconductor device includes a semiconductor substrate and an isolation insulator. A trench is formed on a main surface of the semiconductor substrate. The isolation insulator is formed in an interior of the trench using a thermal oxidation method to isolate element forming regions from each other on the main surface of the semiconductor substrate. The isolation insulator is a lamination body formed by a plurality of oxide film layers.
    Type: Application
    Filed: January 3, 2003
    Publication date: January 29, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mahito Sawada, Hiroshi Tobimatsu, Yoshio Hayashide
  • Publication number: 20020065022
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: August 23, 2001
    Publication date: May 30, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 5840619
    Abstract: An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontally spreading convex pattern and to fill in a concave portion. A portion of insulating film located on a planarized portion of convex pattern is selectively etched away so as to leave a frame-shaped insulating film having a width of 1-500 .mu.m at least on the outer periphery portion of convex pattern. Insulating film left on semiconductor substrate is etched by chemical/mechanical polishing method, thereby planarizing a surface of the semiconductor substrate.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: November 24, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Hayashide
  • Patent number: 5500558
    Abstract: An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontally spreading convex pattern and to fill in a concave portion. A portion of insulating film located on a planarized portion of convex pattern is selectively etched away so as to leave a frame-shaped insulating film having a width of 1-500 .mu.m at least on the outer periphery portion of convex pattern. Insulating film left on semiconductor substrate is etched by chemical/mechanical polishing method, thereby planarizing a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: March 19, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Hayashide
  • Patent number: 5488246
    Abstract: A semiconductor device and method of manufacturing the same includes the steps of forming silicon nitride films including much silicon than a stoichiometric silicon nitride (Si.sub.3 N.sub.4) and which will be an anti-reflection film, forming a resist film on the plasma silicon nitride films and, and concurrently patterning plasma silicon nitride films and conductive layers and using the resist film as a mask. As a result, high integration of the semiconductor device can be attained.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: January 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshio Hayashide, Kouichirou Tsujita
  • Patent number: 5318920
    Abstract: A silicon layer having semispherical protrusions of about 100 nm is formed as a lower electrode of a capacitor by low pressure vapor deposition method. A silicon oxide film is formed by oxidizing the surface of this silicon layer. The intervals between the rough portions of the silicon layer are increased by removing this silicon oxide film. Thereafter, a dielectric layer and an upper electrode are formed. In other methods, after the formation of the silicon layer having the roughness, thermal treatment is continuously carried out in oxygen-free atmosphere to increase radius of curvature of the roughness of the silicon layer. Thereafter, the dielectric layer and the upper electrode are formed.
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: June 7, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Hayashide
  • Patent number: 5290729
    Abstract: A lower electrode of a stacked capacitor in accordance with the present invention is formed of a silicon layer formed by low pressure CVD method. The silicon layer is formed by thermal decomposition of monosilane gas at a prescribed temperature. By setting partial pressure of the monosilane gas and formation temperature at prescribed values, the silicon layer is formed to be in a transitional state between poly crystal and amorphous. Such silicon layer has large concaves and convexes on the surface thereof. Consequently, opposing areas of the electrodes of the capacitor can be increased, and therefore electrostatic capacitance of the capacitor is also increased.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: March 1, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshio Hayashide, Wataru Wakamiya