Patents by Inventor Yoshio Kawamura

Yoshio Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100131093
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Application
    Filed: September 9, 2009
    Publication date: May 27, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Natsuki YOKOYAMA, Yoshifumi KAWAMOTO, Eiichi MURAKAMI, Fumihiko UCHIDA, Kenichi MIZUISHI, Yoshio KAWAMURA
  • Patent number: 7603194
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20080243293
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Application
    Filed: May 28, 2008
    Publication date: October 2, 2008
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7392106
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7310563
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 18, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7062344
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 13, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060111802
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060111805
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 6777337
    Abstract: In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kan Yasui, Souichi Katagiri, Masayuki Nagasawa, Ui Yamaguchi, Yoshio Kawamura
  • Publication number: 20040107020
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Application
    Filed: November 17, 2003
    Publication date: June 3, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 6734103
    Abstract: A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: May 11, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Ui Yamaguchi, Seiichi Kondo, Kan Yasui, Yoshio Kawamura
  • Patent number: 6723144
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: April 20, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Publication number: 20040048554
    Abstract: To solve a problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 11, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Kan Yasui, Masahiko Sato, Souichi Katagiri, Masayuki Nagasawa, Kunio Harada, Satoshi Osabe, Ui Yamaguchi
  • Patent number: 6663468
    Abstract: The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: December 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Kan Yasui, Masahiko Sato, Souichi Katagiri, Masayuki Nagasawa, Kunio Harada, Satoshi Osabe, Ui Yamaguchi
  • Patent number: 6612912
    Abstract: A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: September 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kan Yasui, Souichi Katagiri, Shigeo Moriyama, Yoshio Kawamura, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato
  • Patent number: 6589871
    Abstract: A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Souichi Katagiri, Kan Yasui, Masayuki Nagasawa, Ui Yamaguchi
  • Patent number: 6565424
    Abstract: The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm2.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: May 20, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Yoshio Kawamura, Kan Yasui, Masayuki Nagasawa, Ui Yamaguchi
  • Publication number: 20030084998
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Application
    Filed: December 3, 2002
    Publication date: May 8, 2003
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Patent number: 6524961
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: February 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Publication number: 20020160609
    Abstract: An apparatus comprising a fixed abrasive tool in which fine abrasive grains are uniformly dispersed and fixed, supply systems for processing liquids each containing an oxidizing agent, an organic acid, an inhibitor and purified water, and a sizing dresser capable of dressing the surface of the fixed abrasive tool at a constant size, and adapted to flow a processing liquid for polishing copper at a higher speed in the initial stage of processing, change the polishing liquid to another polishing liquid capable of polishing copper and barrier film substantially at an identical speed just before or just after the exposure of the barrier film and conduct conditioning during processing by driving the sizing dresser, the polishing method and the polishing apparatus enabling to decrease the cost in the existent CMP for planarization of copper wirings requiring two or more steps of CMP, as well as enabling to reduce dishing or erosion resulting in recesses for the wiring shape after planarization, which decrease the s
    Type: Application
    Filed: February 25, 2002
    Publication date: October 31, 2002
    Inventors: Souichi Katagiri, Ui Yamaguchi, Seiichi Kondo, Kan Yasui, Yoshio Kawamura