Patents by Inventor Yoshio Kawashima

Yoshio Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923560
    Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Koyanagi, Yuuko Tomekawa, Takeshi Harada, Yoshio Kawashima
  • Publication number: 20190252488
    Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 15, 2019
    Inventors: TAKAHIRO KOYANAGI, YUUKO TOMEKAWA, TAKESHI HARADA, YOSHIO KAWASHIMA
  • Publication number: 20170152066
    Abstract: A method for manufacturing a packaged medical device includes sealing a packaging bag so that the packaging bag includes a first sub-chamber and a second sub-chamber separated from the first sub-chamber, with the first sub-chamber prevented from communicating with the second sub-chamber. The first sub-chamber contains a medical device and a deoxygenating agent. The first sub-chamber possesses a relatively lower oxygen concentration and the second sub-chamber possesses a relatively higher oxygen concentration. The method also involves communicating the first sub-chamber with the second sub-chamber so that the oxygen concentration in the packaging bag becomes lower than the relatively higher oxygen concentration and higher than the relatively lower oxygen concentration, and irradiating the packaging bag with radiation after the first sub-chamber and the second sub-chamber are in communication with one another.
    Type: Application
    Filed: February 9, 2017
    Publication date: June 1, 2017
    Applicant: TERUMO KABUSHIKI KAISHA
    Inventor: Yoshio KAWASHIMA
  • Publication number: 20170079814
    Abstract: A stent system includes a catheter having a balloon, and a stent mounted on an outer peripheral portion of the balloon. An outer surface of the balloon and an inner surface of the stent have respective modified surfaces, and adhesiveness between the outer surface and the inner surface is improved by the modified surfaces being in contact with each other. A method for manufacturing the stent system includes applying surface treatment to each of the outer surface of the balloon and the inner surface of the stent to modify the outer surface and the inner surface in such a way as to improve adhesiveness outer surface of the balloon and the inner surface of the stent.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: TERUMO KABUSHIKI KAISHA
    Inventor: Yoshio KAWASHIMA
  • Publication number: 20160346072
    Abstract: A protection body protecting the outer circumference of a drug retaining portion, which is provided at a distal portion of a medical elongated body and in which a drug is retained, by covering and sealing the outer circumference, includes a protection layer which is disposed around the outer circumference of the drug retaining portion along the medical elongated body and prevents external oxygen and moisture from coming into contact with the drug retaining portion; and an absorption portion which absorbs oxygen and moisture in a space in the inner circumference of the protection layer and in the outer circumference of the drug retaining portion.
    Type: Application
    Filed: August 9, 2016
    Publication date: December 1, 2016
    Applicant: TERUMO KABUSHIKI KAISHA
    Inventor: Yoshio KAWASHIMA
  • Patent number: 9478584
    Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 25, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshio Kawashima, Yukio Hayakawa, Atsushi Himeno
  • Patent number: 9444044
    Abstract: A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 13, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Hayakawa, Yoshio Kawashima
  • Publication number: 20160000593
    Abstract: A delivery system for a living body indwelling member includes an elongated shaft portion, a stent disposed on a distal side of the shaft portion, and that is caused to indwell a living body, and contrast markers disposed on at least one side of a proximal side or a distal side of the stent, and that have a contrasting property. The contrast markers are arranged up to a position where the contrast markers do not overlap the stent in a separating direction away from the stent from a position where the contrast markers overlap the stent at an axial position of the shaft portion, or from a position where the contrast markers coincide with an edge portion of the stent. Bending rigidity of the contrast markers on the separating direction side is smaller than on a side where the contrast markers come close to the stent.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Applicant: TERUMO KABUSHIKI KAISHA
    Inventor: Yoshio KAWASHIMA
  • Publication number: 20150364681
    Abstract: A nonvolatile storage device includes a first conductive layer disposed on a substrate, a contact plug including a conductive material and disposed on the first conductive layer, a variable resistance element covering the upper surface of the contact plug, resistance of the variable resistance element changing in accordance with an voltage applied to the variable resistance element, one single insulating layer that is directly or indirectly in contact with a sidewall of the contact plug and that is directly or indirectly in contact with a sidewall of the variable resistance element, and a second conductive layer disposed on the variable resistance element.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 17, 2015
    Inventors: HIDEAKI MURASE, YOSHIO KAWASHIMA
  • Patent number: 9184381
    Abstract: A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 10, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Yoshio Kawashima, Shinichi Yoneda
  • Patent number: 9142775
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: September 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Hayakawa, Atsushi Himeno, Hideaki Murase, Yoshio Kawashima, Takumi Mikawa
  • Patent number: 9142773
    Abstract: A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd
    Inventors: Takeki Ninomiya, Takeshi Takagi, Koji Katayama, Yoshio Kawashima
  • Publication number: 20150263279
    Abstract: A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 17, 2015
    Inventors: YUKIO HAYAKAWA, YOSHIO KAWASHIMA
  • Patent number: 9130167
    Abstract: A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: September 8, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno, Takumi Mikawa
  • Patent number: 9082967
    Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer which is in contact with the second electrode; wherein the electrically-conductive layer covers an entire of the second electrode and at least a portion of the side wall protective layer located outward relative to the second electrode, when viewed from a thickness direction; and the side wall protective layer extends across the second electrode to a position above an upper end of the second electrode such that an upper end of the side wall protective layer is located above the upper end of the second electrode, when viewed from a side.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno
  • Patent number: 9076959
    Abstract: A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 7, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Satoru Ito, Yoshio Kawashima, Takumi Mikawa
  • Patent number: 9064570
    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 23, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshio Kawashima, Yukio Hayakawa
  • Publication number: 20150171142
    Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 18, 2015
    Inventors: YOSHIO KAWASHIMA, YUKIO HAYAKAWA, ATSUSHI HIMENO
  • Patent number: 9054305
    Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 9, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Satoru Ito, Yoshio Kawashima, Yukio Hayakawa, Takumi Mikawa
  • Patent number: 9006698
    Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxygen-deficient transition metal oxide, the second electrode has a single needle-shaped part at an interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the single needle-shaped part.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi