Patents by Inventor Yoshio Mizukane

Yoshio Mizukane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8837242
    Abstract: A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Publication number: 20140140155
    Abstract: A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
    Type: Application
    Filed: January 24, 2014
    Publication date: May 22, 2014
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Patent number: 8638625
    Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: January 28, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Patent number: 8618853
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 31, 2013
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20130278310
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Application
    Filed: June 14, 2013
    Publication date: October 24, 2013
    Inventors: Yoshio MIZUKANE, Hiroki FUJISAWA
  • Patent number: 8493110
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 23, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Patent number: 8274843
    Abstract: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Patent number: 8270228
    Abstract: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: September 18, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20120213021
    Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Patent number: 8144524
    Abstract: To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: March 27, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20110279157
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 17, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshio MIZUKANE, Hiroki FUJISAWA
  • Patent number: 8004325
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20110063925
    Abstract: To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 17, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20100302875
    Abstract: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 2, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20100208528
    Abstract: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.
    Type: Application
    Filed: January 28, 2010
    Publication date: August 19, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • Publication number: 20090289677
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 26, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa