Abstract: A semiconductor integrated circuit according to an embodiment includes: a first circuit, an analog-to-digital converter, an external input terminal, a selector, and a second circuit. The first circuit is configured to generate a first voltage corresponding to a temperature. The analog-to-digital converter is configured to convert the first voltage into a first digital value. The external input terminal is a terminal to which a second digital value is input from outside. The selector is configured to select either the first digital value or the second digital value. The second circuit is configured to generate a second voltage based on a third digital value being a digital value selected by the selector.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a first circuit, an analog-to-digital converter, an external input terminal, a selector, and a second circuit. The first circuit is configured to generate a first voltage corresponding to a temperature. The analog-to-digital converter is configured to convert the first voltage into a first digital value. The external input terminal is a terminal to which a second digital value is input from outside. The selector is configured to select either the first digital value or the second digital value. The second circuit is configured to generate a second voltage based on a third digital value being a digital value selected by the selector.

Abstract: A conveyance apparatus includes: a first conveying unit that includes a first conveyance passage along a first direction forming an angle with respect to a horizontal direction, and conveys a medium in the first direction; a returning conveyance unit that conveys the medium towards a second direction having a component of an opposite direction to the first direction; a second conveying unit that includes a second conveyance passage along the second direction, and conveys the medium in the second direction; a first processing unit that is disposed on the first conveyance path, and performs processing on a first surface of the conveying medium; and a second processing unit that is disposed at a position closer to the returning conveyance unit than the first processing unit, and performs processing on a second surface of the conveying medium.

Abstract: A conveyance apparatus includes: a first conveying unit that includes a first conveyance passage along a first direction forming an angle with respect to a horizontal direction, and conveys a medium in the first direction; a returning conveyance unit that conveys the medium towards a second direction having a component of an opposite direction to the first direction; a second conveying unit that includes a second conveyance passage along the second direction, and conveys the medium in the second direction; a first processing unit that is disposed on the first conveyance path, and performs processing on a first surface of the conveying medium; and a second processing unit that is disposed at a position closer to the returning conveyance unit than the first processing unit, and performs processing on a second surface of the conveying medium.

Abstract: According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.

Abstract: According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.

Abstract: A semiconductor memory device includes a memory cell array, in which a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select transistors connected to ends thereof constitute a NAND cell unit, wherein the device has a test mode defined as to detect a read current flowing through the NAND cell unit under the condition of: turning on the first and second select transistors with applying an external voltage to at least one gate of them; simultaneously applying a pass voltage to the entire memory cells in the NAND cell unit to turn on cells without regard to cell data, thereby measuring the property of at least one of the first and second select transistors driven by the external voltage.

Abstract: A semiconductor memory device includes a memory cell array, in which a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select transistors connected to ends thereof constitute a NAND cell unit, wherein the device has a test mode defined as to detect a read current flowing through the NAND cell unit under the condition of: turning on the first and second select transistors with applying an external voltage to at least one gate of them; simultaneously applying a pass voltage to the entire memory cells in the NAND cell unit to turn on cells without regard to cell data, thereby measuring the property of at least one of the first and second select transistors driven by the external voltage.

Abstract: A semiconductor memory device is provided with a determination circuit and an address adder. The determination circuit determines whether a read start address selects upper-address banks B5-B8 or lower-address banks B1-B4. When the determination circuit determines that the lower-address banks are selected, the address adder increments a column address by 1. From the upper-address banks, data are read from the columns corresponding to the read start address. From the lower-address banks, data are read from the columns that are next to the columns corresponding to the read start address. Even when the upper-address banks are designated by the read start address, the data output from the lower-address banks corresponds to the next columns. Since there is no busy time during data output, successive access is enabled and the access cycle time can be as short as possible.

Abstract: Cryptographic key data and data subjected to an operation by use of the cryptographic key data are previously stored in a memory cell array. A memory cell in which the cryptographic key data is stored is accessed and latched and the cryptographic key data is latched in a latch circuit before read out data from the memory cell array. After this, the latched data and data output from a sense amplifier are subjected to an operation by an arithmetical circuit to decode the data and the result of the operation is output as readout data.

Abstract: For copy guard, an ROM comprises an address data determining circuit, an address sequence monitoring circuit, an error address data generating circuit, and an output selection circuit. The address sequence monitoring circuit monitors the addresses stored in the address data determining circuit and input addresses to determine whether or not the input addresses are in a predetermined sequence of the addresses in the address data determining circuit. The output selection circuit outputs data read from said memory cell array when the address sequence monitoring circuit determines that the address sequence of the input addresses coincides with the predetermined sequence of the addresses stored in the address data determining circuit and outputs error data generated by the error data generating circuit when a determination is made that the sequence of the input addresses does not coincide with the predetermined sequence.

Abstract: A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

Abstract: A redundancy memory cell array is arranged at an end of a main memory cell array in the column direction. Common bit lines and common column lines are arranged on the main memory cell array and the redundancy memory cell array. A disconnection circuit is arranged between the main memory cell array and the redundancy memory cell array for connecting or disconnecting bit lines or column lines. A column selection switch is arranged at an end of the redundancy memory cell array. A redundancy circuit disconnects bit lines or column lines by means of a disconnection circuit when an address signal specifies a defective address.

Abstract: A memory system having an input buffer, an address counter, an address decoder, and a memory-cell array. Address signals are supplied to the memory-cell array. In the system, a true-address data determining section has wires or a circuit storing an internal address specific to the system. A false-data generating circuit generates false data when the internal address is in a false data area, and the false data is input to an output selecting circuit. A true-address data area detecting circuit compares the true-address data EAi with the internal address consisting of the address signals supplied from an address counter, and generates a signal REAL when the internal address is in a true-address data area. The output-selecting circuit selects the false data or the data read from the memory-cell array through a sense amplifier, in accordance with whether the signal REAL is at high level or low level. The data stored in the memory-cell array consists of true data items and false data items.

Abstract: A semiconductor integrated circuit includes a chip address data designation circuit, which has nonvolatile circuit characteristics or nonvolatilely programmed wiring corresponding to a chip address assigned to each of semiconductor chips connected to common buses, to output first chip address data corresponding to the chip address upon receiving an operation power supply voltage. The semiconductor integrated circuit further includes a chip address data latch circuit for latching second chip address data supplied from outside to the semiconductor chip, and a chip selection control circuit for comparing the first chip address data and the second chip address data, and generating a chip selection signal for activating the semiconductor chip when the first chip address data and the second chip address data coincide with each other. The chip address assigned to each semiconductor chip can be stored nonvolatilely, and one of the chips can be selected in response to the chip address supplied from outside the chip.

Abstract: In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current.

Abstract: A semiconductor memory includes memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.