Abstract: A transmitting method includes: configuring a frame using a plurality of orthogonal frequency-division multiplexing (OFDM) symbols, by allocating time resources and frequency resources to a plurality of transmission data; and transmitting the frame, wherein the frame includes a first period in which a preamble which includes information on a frame configuration of the frame is transmitted, and a second period in which the plurality of transmission data are transmitted by at least one of time division and frequency division, and among the plurality of OFDM symbols, OFDM symbols included in the second period include pilot symbols arranged along a time axis with a predetermined spacing therebetween, and a predetermined number of data symbols.

Abstract: A transmitting method includes: configuring a frame using a plurality of orthogonal frequency-division multiplexing (OFDM) symbols, by allocating a plurality of transmission data to a plurality of areas; and transmitting the frame. The plurality of areas are each identified by at least one time resource among resources and at least one frequency resource among frequency resources. The frame includes a first period in which a preamble is transmitted, and a second period in which the plurality of transmission data are transmitted by at least one of time division and frequency division. The second period includes a first area, and the first area includes a data symbol generated from first transmission data, a data symbol generated from second transmission data and subsequent to the data symbol generated from the first transmission data, and a dummy symbol subsequent to the data symbol generated from the second transmission data.

Abstract: A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015-1017/cm2 before or after the step of the oxygen ion implantation.

Abstract: A method of manufacturing a semiconductor substrate, in which a silicon layer is provided on a buried oxide film, includes preparing a base substrate having a seed layer of the silicon layer on the buried oxide film with a film thickness equal to or more than 1 nm and equal to or less than 100 nm, and epitaxially growing the seed layer at a temperature equal to or more than 1000° C. and equal to or less than 1300° C. so as to form the silicon layer with a film thickness equal to or more than 1 ?m and equal to or less than 20 ?m.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface of the wafer at an area in which oxygen is implanted, and a rear surface oxide film etching process to treat a rear surface of the wafer, and oxide film etching conditions in the front and rear oxide film etching processes are controlled differently.

Abstract: A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015?1017/cm2 before or after the step of the oxygen ion implantation.

Abstract: A SIMOX wafer is produced at an oxygen ion implantation step and a high-temperature annealing step, wherein an oxide film is formed on a surface of a wafer prior to the oxygen ion implantation and then the oxygen ion implantation is conducted through the oxide film.

Abstract: A SIMOX wafer is produced by implanting oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which a SOI film having a thickness thicker than a target SOI film thickness is previously formed and a final adjustment of the SOI film thickness is carried out at an etching step arranged separately from a cleaning step.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: A method for manufacturing a SOI wafer includes a step of heat-treating a wafer in a furnace to form an SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and a step of unloading the SOI wafer from the furnace maintained at a temperature of 250° C. to 800° C. to transfer the SOI wafer to an atmosphere containing hydrogen or water. The steps are performed in that order.

Abstract: A thermal processing operation is performed for a silicon wafer W (silicon single-crystal layer) in an atmosphere gas which is formed by a hydrogen gas or an inert gas or a mixture gas of these gases at a temperature in a range of 600° C. to 950° C. (here, the temperature should not be greater than 950° C.). By doing this, a quality of a surface of the silicon single-crystal layer is improved.

Abstract: A composition for reducing development defects comprising an acidic composition containing, for example, a surfactant applied onto a chemically amplified photoresist coating formed on a substrate having a diameter of 8 inches or more. By this process, the surface of the resist is rendered hydrophilic and the formation of slightly soluble layer in a developer on the surface of the resist is prevented. In addition, by proper diffusion amount of acid from the composition for reducing development defects, the amount of reduction in thickness of the chemically amplified photoresist coating after development is increased by 10 ? to 500 ? in comparison with the case of not applying the composition for reducing development defects to form a resist pattern not having a deteriorated pattern profile such as T-top or round top.

Abstract: This silicon wafer production process has a step of cutting a silicon wafer from a silicon single crystal ingot in a perfect region which includes a perfect region P free of agglomerates of interstitial-silicon-type point defects and agglomerates of vacancy-type point defects and/or a region R in which there is occurrence of ring-shaped oxidation induced stacking faults, and a step of performing rapid thermal annealing on the silicon wafer in a hydrogen atmosphere, an argon atmosphere or an atmosphere containing a mixed gas thereof.

Abstract: This silicon wafer production process has a step of cutting a silicon wafer from a silicon single crystal ingot in a perfect region which includes a perfect region P free of agglomerates of interstitial-silicon-type point defects and agglomerates of vacancy-type point defects and/or a region R in which there is occurrence of ring-shaped oxidation induced stacking faults, and a step of performing rapid thermal annealing on the silicon wafer in a hydrogen atmosphere, an argon atmosphere or an atmosphere containing a mixed gas thereof.

Abstract: A method for manufacturing a SOI wafer includes a step of heat-treating a wafer in a furnace to form an SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and a step of unloading the SOI wafer from the furnace maintained at a temperature of 250° C. to 800° C. to transfer the SOI wafer to an atmosphere containing hydrogen or water. The steps are performed in that order.

Abstract: A thermal processing operation is performed for a silicon wafer W (silicon single-crystal layer) in an atmosphere gas which is formed by a hydrogen gas or an inert gas or a mixture gas of these gases at a temperature in a range of 600° C. to 950° C. (here, the temperature should not be greater than 950° C.). By doing this, a quality of a surface of the silicon single-crystal layer is improved.

Abstract: A lubrication system for a bearing of a machine. The system comprises an oil tank, and an oil supply pipe for supplying the lubricant oil from the oil tank to the bearing. The system further comprises an outlet pipe for guiding the lubricant oil from the bearing substantially vertically downward so that an outlet pipe oil level may be formed in the outlet pipe. The system further comprises an oil returning mother pipe for guiding the lubricant oil from the outlet pipe to the tank. The oil returning mother pipe includes a substantially horizontal part and a weir or a flow resistance disposed close to the tank so that substantially all portion of the substantially horizontal part may be maintained full of lubricant oil.

Abstract: A lubrication system for a bearing of a machine. The system comprises an oil tank, and an oil supply pipe for supplying the lubricant oil from the oil tank to the bearing. The system further comprises an outlet pipe for guiding the lubricant oil from the bearing substantially vertically downward so that an outlet pipe oil level may be formed in the outlet pipe. The system further comprises an oil returning mother pipe for guiding the lubricant oil from the outlet pipe to the tank. The oil returning mother pipe includes a substantially horizontal part and a weir or a flow resistance disposed close to the tank so that substantially all portion of the substantially horizontal part may be maintained full of lubricant oil.

Abstract: The present invention provides a silicon wafer free of vacancy agglomerates and interstitial agglomerate; wherein the silicon wafer has a defect density of an oxide film of 0.1 piece/cm2 or less, when the oxide film having a thickness of 5 to 25 nm is formed on the surface of the wafer and a DC voltage of 10 MV/cm is applied via the oxide film for 100 seconds, and wherein the silicon wafer has an in-plane dispersion of 20% or less of a p-n junction leakage current in a p-n junction area of 1 mm2 or more of a p-n junction portion when the p-n junction portion is formed on the surface of the wafer. The present silicon wafer is capable of achieving a higher performance, higher yield and uniformity of characteristics of semiconductor devices comparable to a wafer provided with a pure epitaxial layer, without deteriorating the gettering ability of the silicon wafer.