Abstract: In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.

Abstract: In addition to two-stage CMOS inverters for inverting and amplifying the input signal IN, a rising edge detector 3 for detecting the rising edge of the input signal IN, and outputting a rising edge detection signal S3 having a pulse width corresponding to the ambient temperature, and a PMOS 5 for driving the output node NO to the power supply potential VDD according to the rising edge detection signal S3, and the falling edge detector 4 for detecting the falling edge of the input signal IN and outputting a falling edge detection signal S4 having a pulse width corresponding to the ambient temperature, and an NMOS 6 driving the output node NO to the ground potential GND according to the falling edge detection signal S4.

Abstract: A control signal generating circuit for generating control signals, based on a first clock signal, a second clock signal and a mode setting signal, and a plurality of scanpath circuits. Operation of each of the scanpath circuits is controlled according to the generated control signals. The control signal generating circuit and scanpath circuits are provided in a semiconductor integrated circuit having reduced size.

Abstract: A processing unit for executing parallel cumulative absolute difference operations in a first mode, and an inner product operation in a second mode, includes an input bus group for receiving first input data, second input data, and third input data. A plurality of processor elements are coupled to the input bus group, each processor element being coupled to compute a cumulative absolute difference between the first input data and the second input data in the first mode, and to compute and accumulate one term of Booth's algorithm for multiplying the first input data by the third input data in the second mode. An output bus group is coupled to the processor elements, for receiving the terms of Booth's algorithm. An accumulator circuit is coupled to the output bus group, for shifting and adding terms of Booth's algorithm output by the processor elements.

Abstract: An absolute value arithmetic circuit for computing the absolute value of two binary input signals, includes: a computing circuit for obtaining a difference between the two input signals, a 1's complementor for non-inverting or inverting an output from the computing circuit in accordance with a positive sign bit or a negative sign bit of the output, a priority encoder for searching an output from the 1's complementor for the position of a first "0" bit from the least significant digit of the output and delivering an encoder output indicating the position of the first "0" bit, and a bit inverting circuit for inverting and delivering a bit row from the least significant digit bit to the "0" bit in the output from the 1's complementor in accordance with the encoder output, and directly delivering a bit row from a bit higher than the "0" bit to the most significant digit bit of the output without inverting them.