Abstract: According to one embodiment of the present invention, there is provided a system for allocating bandwidth in a network to a plurality of traffic classes. Each traffic class has a first bandwidth allocation. The system comprises a network manager which is configured to determine a bandwidth utilization for each traffic class, to determine an amount of unused network bandwidth, to calculate second bandwidth allocations for each traffic class by allocating a share of any determined unused network bandwidth between at least some of the traffic classes, and to update, in accordance with the second bandwidth allocations, a routing table accessible by routers in the network.

Abstract: Example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method involves enabling a sharing of a memory page of a source domain executing on a first virtual machine with a destination domain executing on a second virtual machine. The example method also involves mapping the memory page to an address space of the destination domain and adding an address translation entry for the memory page in a table. In addition, the example method involves sharing the memory page with a hardware device for direct memory access of the memory page by the hardware device.

Abstract: In a method (400) for routing packets between a plurality of top switches (110a-110n) and a plurality of leaf switches (120a-120n) using a balancing table (204, 208, 210) in a fat tree network (100), a failed link between at least one top switch (110n) and at least one leaf switch (120n) is detected (402). In addition, the balancing table (204, 208, 210) is modified (406) based on the detected failed link, and the packets are routed (408) between the plurality of top switches (110a-110n) and the plurality of leaf switches (120a-120n) in the fat tree network (100) based on the modified balancing table (204, 208, 210).

Abstract: Packet processing for packets from a virtual machine includes receiving a packet from an external switch at a computer system hosting a plurality of virtual machines. If the received packet is a learning packet, storing a packet signature determined from the learning packet. For a packet to be transmitted from a virtual machine in the computer system, determining if the packet's signature matches the stored packet signature. If the packet's signature matches the stored packet signature, performing an action associated with the packet signature.

Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.

Abstract: Illustrated is a system and method to generate a teaching message with a host device address that impersonates a device source address, the impersonation to instruct an additional network device as to the host device address. It further include a transmitter to transmit the teaching message to the additional network device. It also includes traversing a forwarding table to identify an additional network device that has yet to receive a teaching message since an expiration of a predefined threshold value, the teaching message to relate to a source device. It also includes a transmitter to transmit a teaching message to the additional network device.

Abstract: Example embodiments relate to selective invalidation of packet filtering cache results based on rule priority. In example embodiments, a network node determines whether a rule identifier included in a cache entry of a cache of results of a packet filtering rule set is of a higher priority than a highest priority rule corresponding to a rule set version identifier included in the cache entry. If so, the network node may apply an action included in the cache entry.

Abstract: In a method for managing a data structure in a memory, an accessor to access a version of the data structure is determined, in which the accessor includes a version number and a fat pointer, in which the version number corresponds to the most recent version of the data structure, and wherein the fat pointer is configured to enable for multiple versions of a linked-data structure to be maintained.

Abstract: A system and method for selecting a preferred design for a multi-tiered architecture of components based on a set of established criteria is provided. The system and method receive a model describing different design constructions and a set of performance and availability requirements and produces a design or set of designs that best meet these requirements. The system and method include a model for representing the infrastructure design space for multi-tier systems and their properties appropriate for judging performance and availability properties of services as well as associated cost. The method and system further include a method for searching the design space in an efficient manner.

Abstract: Illustrated is a system for performing Deep Packet Inspection (DPI) that includes a core to prepare a data packet for transmission. Further, the system includes a memory controller to direct the data packet to a DPI core. Additionally, the system includes a Network Interface Card to receive the data packet for transmission after DPI is performed on the data packet by the DPI core. The system includes a Direct Memory Management module to update a descriptor that references a received data packet stored in an Operating System buffer. Moreover, the system includes an Input/Output Memory Management Unit to direct the descriptor to be stored in a DPI memory. Additionally, the system includes an interrupt controller to transmit an interrupt to the DPI core to such that the DPI core retrieves the descriptor from the DPI memory and performs DPI on the data packet stored in the OS buffer.

Abstract: Example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method involves enabling a sharing of a memory page of a source domain executing on a first virtual machine with a destination domain executing on a second virtual machine. The example method also involves mapping the memory page to an address space of the destination domain and adding an address translation entry for the memory page in a table. In addition, the example method involves sharing the memory page with a hardware device for direct memory access of the memory page by the hardware device.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.

Abstract: In a method for routing packets between a plurality of switches in a computer network, in which paths between the plurality of switches are identified as a plurality of virtual local area networks (VLANs) stored in a balancing table, a packet to be routed from a source switch to a destination switch is received. In addition, a VLAN is selected from the plurality of VLANs in the balancing table to route the packet through the computer network and the packet is routed through the selected VLAN.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.

Abstract: According to one embodiment of the present invention, there is provided a system for allocating bandwidth in a network to a plurality of traffic classes. Each traffic class has a first bandwidth allocation. The system comprises a network manager which is configured to determine a bandwidth utilization for each traffic class, to determine an amount of unused network bandwidth, to calculate second bandwidth allocations for each traffic class by allocating a share of any determined unused network bandwidth between at least some of the traffic classes, and to update, in accordance with the second bandwidth allocations, a routing table accessible by routers in the network.

Abstract: In a method for processing packets among at least a first computing device and a second computing device, in which the first computing device is configured to transmit and receive packets through a Network Interface Card (NIC), in the second computing device, descriptors of packets to be one of transmitted and received by the first computing device through a device descriptor queue are received and placed in a virtualized descriptor queue accessible by the second computing device. In addition, the packets associated with the descriptors placed in the virtualized descriptor queue are processed prior to one of transmission and receipt of the packets by the first computing device.

Abstract: A first virtual machine is implemented on one or more computing devices to generate input/output (I/O) requests to a hardware device. A second virtual machine is also implemented on the computing devices. A mechanism is to switch between a direct mode and an indirect mode without switching between a first context and a second context of the hardware device. In the direct mode, the I/O requests generated by the first virtual machine are to be sent to the hardware device without being redirected to the second virtual machine. In the indirect mode, the I/O requests generated by the first virtual machine are to be redirected to the second virtual machine for processing. The second virtual machine is to, after processing the I/O requests redirected to the second virtual machine, send the I/O requests to the hardware device.

Abstract: A network controls congestion by monitoring how well packets are actually being received at their respective dataflow destinations. The destination nodes are outfitted with a monitor that returns an acknowledgement (ACK) datapacket to the source node for each reception. The return ACK datapackets are marked according to whether congestion was encountered in the delivery to the destination. If so, a rate limiter at the source node is signaled to slow down the data injection rate. If not, the rate limiter is signaled to dial up the injection rate. Several dataflows can be independently and simultaneously controlled this way.

Abstract: Illustrated is a system for performing Deep Packet Inspection (DPI) that includes a core to prepare a data packet for transmission. Further, the system includes a memory controller to direct the data packet to a DPI core. Additionally, the system includes a Network Interface Card to receive the data packet for transmission after DPI is performed on the data packet by the DPI core. The system includes a Direct Memory Management module to update a descriptor that references a received data packet stored in an Operating System buffer. Moreover, the system includes an Input/Output Memory Management Unit to direct the descriptor to be stored in a DPI memory. Additionally, the system includes an interrupt controller to transmit an interrupt to the DPI core to such that the DPI core retrieves the descriptor from the DPI memory and performs DPI on the data packet stored in the OS buffer.

Abstract: A system and method for selecting a preferred design for a multi-tiered architecture of components based on a set of established criteria is provided. The system and method receive a model describing different design constructions and a set of performance and availability requirements and produces a design or set of designs that best meet these requirements. The system and method include a model for representing the infrastructure design space for multi-tier systems and their properties appropriate for judging performance and availability properties of services as well as associated cost. The method and system further include a method for searching the design space in an efficient manner.