Patents by Inventor Yoshioka Hiroshi

Yoshioka Hiroshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ENHANCING THE FUNCTION IMMUNOCYTES AND HEMOCYTES USING TGP AND MICROGRAVITY
    Publication number: 20190085290
    Abstract: Method of enhancing the cellular functions characterized by the inclusion of at least the process, wherein the aqueous solution containing the cells in the low temperature sol state, in an aqueous solution that exhibits thermoreversible sol-gel transition of being a sol at low temperatures and gel at high temperatures containing at least a hydrogel-forming polymer, bringing the solution containing the to a high temperature gel and then culturing the cells under microgravity.
    Type: Application
    Filed: March 14, 2017
    Publication date: March 21, 2019
    Inventors: Mori YUICHI, Yoshioka HIROSHI, Terunuma HIROSHI, Abraham SAMUEL
  • Semiconductor memory device with reduced power consumption and with reduced test time
    Patent number: 6560138
    Abstract: A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the ac
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: May 6, 2003
    Assignee: Fujitsu Limited
    Inventors: Kouichi Noro, Yoshioka Hiroshi
  • Semiconductor memory device with reduced power consumption and with reduced test time
    Publication number: 20020024840
    Abstract: A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the ac
    Type: Application
    Filed: October 22, 2001
    Publication date: February 28, 2002
    Applicant: Fujitsu Limited
    Inventors: Kouichi Noro, Yoshioka Hiroshi
  • Semiconductor memory device with reduced power consumption and with reduced test time
    Patent number: 6330180
    Abstract: A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the ac
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: December 11, 2001
    Assignee: Fujitsu Limited
    Inventors: Kouichi Noro, Yoshioka Hiroshi
  • Semiconductor memory device with reduced power consumption and with reduced test time
    Publication number: 20010026467
    Abstract: A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the ac
    Type: Application
    Filed: January 29, 2001
    Publication date: October 4, 2001
    Applicant: Fujitsu Limited
    Inventors: Kouichi Noro, Yoshioka Hiroshi