Abstract: A data processing apparatus includes a plurality of computation devices connected to each other by a communication path. Each of the computation devices includes: a switching section provided to each of terminals and switchable between an upper layer use state in which communication is performed by a communication section between a given terminal of a plurality of terminals and a corresponding internal path and there is no connection performed by a bypass section between a corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by a communication section between the given terminal of the plurality of the terminals and the corresponding internal path and connection is performed by the bypass section between the corresponding pair of the plurality of the terminals.

Abstract: A processor includes a plurality of nodes arranged two dimensionally in the X-axis direction and in the Y-axis direction, and each of the nodes includes a processor core and a distributed shared cache memory. The processor also includes a first connecting unit and a second connecting unit. The first connecting unit connects adjacent nodes in the X-axis direction among the nodes, in a ring shape. The second connecting unit connects adjacent nodes in the Y-axis direction among the nodes, in a ring shape. The cache memories included in the respective nodes are divided into banks in the Y-axis direction. Coherency of the cache memories in the X-axis direction is controlled by a snoop system. The cache memories are shared by the nodes.

Abstract: An operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory configured to store the first data and third data, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first, second and third data, wherein when the setting unit sets the operation processing unit to the non-operating state and the third data is requested from another operation processing apparatus, which triggers cache miss in the cache memory, the control unit reads the requested data from the main memory and holds the requested data in the cache memory and sends the read data to another operation processing apparatus.

Abstract: An operation processing apparatus connected with another operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by another operation processing apparatus and acquired from another operation processing apparatus, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first data and the second data, wherein when the setting unit sets the operation processing unit to the operating state and the second data is evicted from the cache memory, the control unit sends to another operation processing apparatus the evicted data and a request which is a trigger for storing the evicted data in a cache memory in another operation processing apparatus.

Abstract: A processor includes a plurality of nodes arranged two dimensionally in the X-axis direction and in the Y-axis direction, and each of the nodes includes a processor core and a distributed shared cache memory. The processor also includes a first connecting unit and a second connecting unit. The first connecting unit connects adjacent nodes in the X-axis direction among the nodes, in a ring shape. The second connecting unit connects adjacent nodes in the Y-axis direction among the nodes, in a ring shape. The cache memories included in the respective nodes are divided into banks in the Y-axis direction. Coherency of the cache memories in the X-axis direction is controlled by a snoop system. The cache memories are shared by the nodes.

Abstract: A network performance estimating device for estimating network performance of a parallel computing machine for executing plural processes in parallel, includes a communication data obtaining unit that obtains communication data output from plural calculation nodes when the plural processes are executed by using the plural calculation nodes, a design estimating unit for referring to a design information storing unit that stores design information defining a network as an estimation target to execute a simulation on communications when the communication data obtained by the communication data obtaining unit are transmitted through the network as the estimation target, and renews estimation information representing an estimation result of the estimation target network stored by an estimation information storing unit on the basis of the obtained simulation result, and a communication data transmission unit for transmitting the communication data obtained by the communication data obtaining unit to an addressed ca

Abstract: A data processing apparatus includes a plurality of computation devices connected to each other by a communication path. Each of the computation devices includes: a switching section provided to each of terminals and switchable between an upper layer use state in which communication is performed by a communication section between a given terminal of a plurality of terminals and a corresponding internal path and there is no connection performed by a bypass section between a corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by a communication section between the given terminal of the plurality of the terminals and the corresponding internal path and connection is performed by the bypass section between the corresponding pair of the plurality of the terminals.

Abstract: The data transmitting device receives data from a plurality of computation nodes transmitting data each other. The data transmitting device acquires a cumulative number of other data being counterparts of adjustment performed by the computation nodes until the data is received from each received data. The data transmitting device updates the cumulative number acquired from each data, on the basis of a number of the received data. The data transmitting device selectes data to be transmitted to the computation nodes by adjusting the received on the basis of the updated cumulative number. The data transmitting device stores the updated cumulative number in the selected data. The data transmitting device transmits the data in which the cumulative number is stored to the other device.

Abstract: In a blade of a blade server, power is supplied from a power distributing unit to an internal circuit, and also supplied to a capacitor to charge the capacitor. If power consumption of the blade server is high and a process load on a blade is also high, power is supplied to the internal circuit from both the power distributing unit and the capacitor. If the process load on the blade is low, power is supplied to the internal circuit only from the power distributing unit.

Abstract: An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

Abstract: A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

Abstract: A network performance estimating device for estimating network performance of a parallel computing machine for executing plural processes in parallel, includes a communication data obtaining unit that obtains communication data output from plural calculation nodes when the plural processes are executed by using the plural calculation nodes, a design estimating unit for referring to a design information storing unit that stores design information defining a network as an estimation target to execute a simulation on communications when the communication data obtained by the communication data obtaining unit are transmitted through the network as the estimation target, and renews estimation information representing an estimation result of the estimation target network stored by an estimation information storing unit on the basis of the obtained simulation result, and a communication data transmission unit for transmitting the communication data obtained by the communication data obtaining unit to an addressed ca

Abstract: A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

Abstract: An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

Abstract: In a blade of a blade server, power is supplied from a power distributing unit to an internal circuit, and also supplied to a capacitor to charge the capacitor. If power consumption of the blade server is high and a process load on a blade is also high, power is supplied to the internal circuit from both the power distributing unit and the capacitor. If the process load on the blade is low, power is supplied to the internal circuit only from the power distributing unit.

Abstract: The present invention has been made to provide a computer management program, a managed computer control program, a computer management apparatus, a managed computer, a computer management system, a computer management method, and a managed computer control method allowing the management agent to easily perform autonomous communication frequency control.