Patents by Inventor Yoshiro Suemitsu

Yoshiro Suemitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230215751
    Abstract: An operating method of a vacuum processing apparatus for processing multiple wafers sequentially in a vacuum processing apparatus comprising multiple vacuum transfer containers, adjacent two of which are interlinked, a lock chamber inside which a wafer is housed. The multiple processing units are each subjected to of cleaning the interior thereof upon elapse of a predetermined period. In advance of processing multiple wafers, the operating method configures multiple sets of processing units to process each of the wafers from among the multiple processing units and starts processing of the wafers, delayed by a predetermined time in descending order of the number of processing units included in each of the multiple sets of processing units and in descending order of distance of the processing units included from the lock chamber.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 6, 2023
    Inventors: Daichi Naiki, Yoshiro Suemitsu, Shinichiro Numata
  • Patent number: 11164766
    Abstract: Provided is a technique capable of implementing efficient transport and processing related to multi-step processing in the case of a link-type vacuum processing apparatus with related to an operating method of a vacuum processing apparatus. The operating method of the vacuum processing apparatus according to the embodiment, in order to minimize time required for all processing of a plurality of wafers in a multi-step processing, includes a first step (steps 601 to 607) of selecting one first processing unit and one second processing unit from a plurality of processing units for each wafer and determining a transport schedule including a transport path using the selected processing units. In the first step, for at least one wafer, a transport schedule including a transport path is configured using the selected first processing unit by excluding at least one first processing unit from the plurality of first processing units.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 2, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Yoshikazu Saigou, Yoshiro Suemitsu, Hiroyuki Ishikawa
  • Publication number: 20210151336
    Abstract: Provided is a technique capable of implementing efficient transport and processing related to multi-step processing in the case of a link-type vacuum processing apparatus with related to an operating method of a vacuum processing apparatus. The operating method of the vacuum processing apparatus according to the embodiment, in order to minimize time required for all processing of a plurality of wafers in a multi-step processing, includes a first step (steps 601 to 607) of selecting one first processing unit and one second processing unit from a plurality of processing units for each wafer and determining a transport schedule including a transport path using the selected processing units. In the first step, for at least one wafer, a transport schedule including a transport path is configured using the selected first processing unit by excluding at least one first processing unit from the plurality of first processing units.
    Type: Application
    Filed: February 7, 2019
    Publication date: May 20, 2021
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Yoshikazu SAIGOU, Yoshiro SUEMITSU, Hiroyuki ISHIKAWA
  • Patent number: 9257318
    Abstract: A method for operating a vacuum processing apparatus, the vacuum processing apparatus including: a plurality of cassette stands on which a cassette capable of housing a plurality of wafers therein can be placed; a plurality of vacuum processing vessels each having a processing chamber arranged therein, wherein the wafer is arranged and processed in the processing chamber; and at least one transport robot transporting the wafer on a transport path between either one of the plurality of cassettes and the plurality of vacuum processing vessels, the vacuum processing apparatus sequentially transporting in a predetermined transport order the plurality of wafers from either one of the plurality of cassettes to a predetermined one of the plurality of vacuum processing vessels and processing the plurality of wafers. The method includes a number determining step, a remaining-time determining step and a transport order skip step.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 9, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Michinori Kawaguchi, Satomi Inoue, Yoshiro Suemitsu, Keita Nogi
  • Publication number: 20140294555
    Abstract: A method for operating a vacuum processing apparatus, the vacuum processing apparatus including: a plurality of cassette stands on which a cassette capable of housing a plurality of wafers therein can be placed; a plurality of vacuum processing vessels each having a processing chamber arranged therein, wherein the wafer is arranged and processed in the processing chamber; and at least one transport robot transporting the wafer on a transport path between either one of the plurality of cassettes and the plurality of vacuum processing vessels, the vacuum processing apparatus sequentially transporting in a predetermined transport order the plurality of wafers from either one of the plurality of cassettes to a predetermined one of the plurality of vacuum processing vessels and processing the plurality of wafers. The method includes a number determining step, a remaining-time determining step and a transport order skip step.
    Type: Application
    Filed: August 26, 2013
    Publication date: October 2, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Michinori KAWAGUCHI, Satomi INOUE, Yoshiro SUEMITSU, Keita NOGI
  • Publication number: 20140099176
    Abstract: A semiconductor processing apparatus is provided, which includes processing chambers coupled together by transport mechanisms having transfer robots. After having completed wafer processing in each processing chamber, the allowable value of a time permitted for a processing-completed wafer to continue residing within the processing chamber is set up. Then, a time consumed up to the completion of transportation of a wafer scheduled to be next processed is estimated, thereby controlling a transfer robot in a way such that, when the estimated transfer time exceeds the allowable value of the waiting time, priority is given to an operation for unloading a processed wafer from the processing chamber insofar as the processed wafer's transfer destination is already in its state capable of accepting such wafer.
    Type: Application
    Filed: September 11, 2013
    Publication date: April 10, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Keita NOGI, Teruo NAKATA, Kenji TAMAI, Michinori KAWAGUCHI, Yoshiro SUEMITSU
  • Patent number: 8588962
    Abstract: Transportation control in a vacuum processing device with high transportation efficiency without lowering throughput is provided. A control unit is configured to update in real time and holds device state information showing an action state of each of a process chamber, a transportation mechanism unit, a buffer room, and a holding mechanism unit, the presence of a process subject member, and a process state thereof; select a transport algorithm from among transport algorithm judgment rules that are obtained by simulating in advance a plurality of transport algorithms for controlling transportation of a process subject member for each condition of a combination of the number and arrangement of the process chambers and process time of a process subject member based on the device state information and process time of the process subject member; and compute a transport destination of the process subject member based on the selected transport algorithm.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 19, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Keita Nogi, Teruo Nakata, Yoshiro Suemitsu, Michinori Kawaguchi, Satomi Inoue