Patents by Inventor Yoshisato Yokohama

Yoshisato Yokohama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100277970
    Abstract: Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P1 and P2 and gate electrodes of the load transistors PL1 and PL2 are connected at the node 1 and the node 2. A source electrode of the additional transistor P1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S1 and S2 to the H level in other times than data write so that the additional transistor P1 or P2 compensates the load transistor PL1 or PL2, thereby increasing the static margin.
    Type: Application
    Filed: July 13, 2010
    Publication date: November 4, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takuya Hayashi, Yoshisato Yokohama