Patents by Inventor Yoshishige Matsumoto

Yoshishige Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030207125
    Abstract: After a GaN film 12 is formed on a (0001) plane sapphire (Al2O3) substrate 11, islands of the GaN film 12 are formed by wet etching. An upper part of the islands of the GaN film 12 is a single-crystal layer. By performing epitaxial growth over the islands of GaN film 12, a GaN film 15 with little crystal defect is obtained.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 6, 2003
    Applicant: NEC CORPORATION
    Inventors: Haruo Sunakawa, Yoshishige Matsumoto, Akira Usui
  • Patent number: 6372628
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Patent number: 6252261
    Abstract: A GaN crystal film having a mask patterned in a stripe for forming multiple growing areas on a sapphire substrate and coalesced GaN crystals covering the mask dividing the areas, grown from the neighboring growing areas, comprising defects where multiple dislocations along with the stripe are substantially aligned with the normal line of the substrate, in the crystal areas over the mask, and dislocations propagating in substantially parallel with the substrate surface while, in the vicinity of the areas where the crystals are coalesced over the mask, propagating substantially in the normal line of the substrate surface, and a manufacturing process therefor. According to this invention, there can be provided a GaN crystal film in which strain, defects and dislocations are reduced and which tends not to generate cracks.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 26, 2001
    Assignee: NEC Corporation
    Inventors: Akira Usui, Akira Sakai, Haruo Sunakawa, Masashi Mizuta, Yoshishige Matsumoto
  • Patent number: 6180531
    Abstract: A semiconductor device, in which wiring layers are electrically isolated from each other by an insulating film which includes an amorphous carbon fluoride film insulating film containing carbon and fluorine as main components and the wiring layers are electrically connected to each other by a conductive material buried in a hole penetrating through the insulating film, is manufactured by selectively etching the amorphous carbon fluoride film. Moreover, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on both of the amorphous carbon fluoride film and a side surface of said hole, or one of the amorphous carbon fluoride film and the side surface thereof.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: January 30, 2001
    Assignee: NEC Corporation
    Inventors: Yoshishige Matsumoto, Yoshitake Ohnishi, Kazuhiko Endo, Toru Tatsumi
  • Patent number: 6091081
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Patent number: 5866920
    Abstract: A semiconductor device, in which wiring layers are electrically isolated from each other by an insulating film which includes an amorphous carbon fluoride film insulating film containing carbon and fluorine as main components and the wiring layers are electrically connected to each other by a conductive material buried in a hole penetrating through the insulating film, is manufactured by selectively etching the amorphous carbon fluoride film. Moreover, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on both of the amorphous carbon fluoride film and a side surface of said hole, or one of the amorphous carbon fluoride film and the side surface thereof.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: February 2, 1999
    Assignee: NEC Corporation
    Inventors: Yoshishige Matsumoto, Yoshitake Ohnishi, Kazuhiko Endo, Toru Tatsumi
  • Patent number: 4689646
    Abstract: The depletion mode two-dimensional electron gas field effect transistor comprises a substantially pure semiconductor layer, an impurity doped super lattice semiconductor layer formed on the pure semiconductor layer, the energy band gaps and the electron affinities of the pure semiconductor layer and the super lattice semiconductor layer being selected to produce the two-dimensional electron gas at the surface of the pure semiconductor layer when no bias is applied to the super lattice semiconductor layer, source and drain regions formed separatedly in the super lattice semiconductor layer to reach the pure semiconductor layer, a gate electrode formed on the super lattice semiconductor layer between the source and drain regions, and large energy band gap regions formed at side portions of the gate electrode which do not face the source and drain regions, the large energy band gap regions having an energy band gap larger than the super lattice semiconductor layer and being formed by local annealing to convert t
    Type: Grant
    Filed: June 5, 1985
    Date of Patent: August 25, 1987
    Assignee: NEC Corporation
    Inventors: Yoshishige Matsumoto, Naotaka Iwata
  • Patent number: 4434491
    Abstract: A semiconductor laser of the rib guide type having the thickness of an active layer within a stripe-shaped region thicker than that of the outside, and thus the stripe-shaped region is made to have a waveguide action and, thereby, fundamental mode laser may be achieved.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: February 28, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Isamu Sakuma, Katsuhiko Nishida, Hideo Kawano, Masayasu Ueno, Yoshishige Matsumoto, Shohei Matsumoto, Takao Furuse