Abstract: In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102).

Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.

Abstract: A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.

Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.

Abstract: In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102).

Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.

Abstract: A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

Abstract: An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.

Abstract: An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.

Abstract: A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

Abstract: Excessive CMP (chemical mechanical polishing) of a resistive band region and margin deterioration in processing in a subsequent step are prevented, while a resistive zone is formed with an active region. In the semiconductor device, a source/drain impurity diffusion layer is used as the resistive zone. On a semiconductor substrate, the resistive band region to form the resistive zone, having at least a portion of a surface provided as the active region, is formed. In the resistive band region, the resistive zone is provided. A word line is arranged on the semiconductor substrate so as to surround the resistive zone. In the resistive band region, the area occupancy ratio of the active region per 10 &mgr;m□ is set to be 40% or higher.

Abstract: A photomask includes patterns corresponding to openings, a pattern corresponding to a trench and dummy patterns not to be transferred to a photoresist. The patterns are arranged in a matrix at a second pitch in the column direction and at a first pitch in the row direction. The dummy patterns are spaced at the second pitch from the most adjacent ones of the patterns aligned in the row direction, and the dummy patterns are spaced at a first pitch from the most adjacent ones of the patterns aligned in the column direction. Using such photomask, openings on each of which a lower electrode of a capacitor is to be formed are formed in an insulation layer in a memory cell array forming region, and the trench is formed in the insulation layer at the border between the memory cell array forming region and a peripheral circuit forming region.

Abstract: An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.

Abstract: A photomask (34) includes patterns (40) corresponding to openings, a pattern (41) corresponding to a trench and dummy patterns (50-55) not to be transferred to a photoresist. The patterns (40) are arranged in a matrix at a pitch P2 in the column direction and at a pitch P1 in the row direction. The dummy patterns (50) are spaced at the pitch P2 from the most adjacent ones of the patterns (40) aligned in the row direction, and the dummy patterns (51) are spaced at the pitch P1 from the most adjacent ones of the patterns (40) aligned in the column direction. Using such photomask (34), openings on each of which a lower electrode of a capacitor is to be formed are formed in an insulation layer in a memory cell array forming region, and the trench is formed in the insulation layer at the border between the memory cell array forming region and a peripheral circuit forming region.

Abstract: There can be provided a semiconductor device having a rough surface to provide an increased capacitance of a capacitor and enhanced prevention of short-circuit between capacitors, and a method of manufacturing the same. The semiconductor device includes a plug interconnection penetrating an insulating film and connected to an underlying wiring, and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion of the storage node without covering a side surface of the lower portion of the storage node, and having a rough surface.

Abstract: Excessive CMP (chemical mechanical polishing) of a resistive band region and margin deterioration in processing in a subsequent step are prevented, while a resistive zone is formed with an active region. In the semiconductor device, a source/drain impurity diffusion layer is used as the resistive zone. On a semiconductor substrate, the resistive band region to form the resistive zone, having at least a portion of a surface provided as the active region, is formed. In the resistive band region, the resistive zone is provided. A word line is arranged on the semiconductor substrate so as to surround the resistive zone. In the resistive band region, the area occupancy ratio of the active region per 10 &mgr;m□ is set to be 40% or higher.

Abstract: There can be provided a semiconductor device having a rough surface to provide an increased capacitance of a capacitor and enhanced prevention of short-circuit between capacitors, and a method of manufacturing the same. The semiconductor device includes a plug interconnection penetrating an insulating film and connected to an underlying wiring, and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion of the storage node without covering a side surface of the lower portion of the storage node, and having a rough surface.

Abstract: In a method of manufacturing a semiconductor device, a silicon oxide film is embedded in a trench portion for isolating the device forming regions on a silicon substrate, and a silicon nitride film, a polysilicon film, and a pad insulating film left on the device forming regions on a silicon substrate are removed to expose a surface of the semiconductor substrate, wherein the polysilicon film is removed by isotropic wet etching.

Abstract: A method of manufacturing a semiconductor devices includes the formation of a pad insulating film, a polysilicon film and a silicon nitride film on a semiconductor substrate. A trench portion is formed in the substrate after etching, and silicon oxide is embedded in the trench portion. The silicon nitride film, polysilicon film, and pad insulating film are then removed to expose a surface of the semiconductor substrate. The removal of the polysilicon film is by isotropic wet etching. A circuit element is formed on the exposed surfaces of the semiconductor substrate.

Abstract: An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.