Patents by Inventor Yoshitaka Furukawa

Yoshitaka Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145122
    Abstract: An insulated electric wire containing a conductor having a flat shape and showing excellent selectivity for bending in the height direction of the flat shape, and a wiring harness containing such an insulated electric wire. An insulated electric wire contains a conductor and an insulation cover covering an outer periphery of the conductor. The conductor contains a flat portion which has a flat shape, in a cross section perpendicular to an axial direction of the conductor, having a larger size in a width direction than in a height direction. In the flat portion, a flexural rigidity in the width direction x of the insulated electric wire is 2.6 times or more than a flexural rigidity in the height direction y. The wiring harness contains the insulated electric wire.
    Type: Application
    Filed: March 29, 2022
    Publication date: May 2, 2024
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toru SHIMIZU, Toyoki FURUKAWA, Kyoma SAHASHI, Yoshitaka YAMADA
  • Publication number: 20240145123
    Abstract: An insulated electric wire includes a flat portion and a low-flatness portion along an axial direction x, having elemental wires constituting a conductor and an insulation coating being continuous with one another. An outer shape of the conductor of the flat portion in a cross-section perpendicular to the axial direction x of the insulated electric wire takes a flat shape, and an outer shape of the conductor of the low-flatness portion takes a shape with flatness lower than the flat portion. In each of the cross-sections of the conductor of the flat portion and the low-flatness portion, deformation ratios of the elemental wires from a circle at width directional end parts, which corresponds to regions facing an outer periphery of the conductor at both ends of the flat shape in a width direction, are lower than the deformation ratios of the elemental wires at a center parts of the conductor.
    Type: Application
    Filed: March 25, 2022
    Publication date: May 2, 2024
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kyoma SAHASHI, Toyoki FURUKAWA, Yoshitaka YAMADA
  • Patent number: 4128815
    Abstract: In single transverse mode semiconductor lasers, a semiconductor laser which comprises an optical confinement semiconductor layer having a refractive index of n.sub.3, an active layer of an optical waveguide having a refractive index of n.sub.1 and formed on said semiconductor layer, a buffer layer having a refractive index of n.sub.2 and formed on said active layer, a mode controlling striped semiconductor layer having a refractive index of n.sub.6 and formed on said buffer layer and opposing contacts, and is controllable in the transverse mode in the relations ofn.sub.6 .ltoreq.n.sub.2 <n.sub.1 and n.sub.3 <n.sub.1.
    Type: Grant
    Filed: September 23, 1976
    Date of Patent: December 5, 1978
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventors: Hitoshi Kawaguchi, Yoshitaka Furukawa
  • Patent number: 4030949
    Abstract: Disclosed is a method of yielding a multilayer-liquid phase epitaxial growth of Al.sub.x Ga.sub.1.sub.-x As and GaAs for manufacturing a double heterostructure laser, light emitting diode, etc., which is characterized in that hydrogen gas or inert gas, containing GaCl gas, is used as an atmosphere for the epitaxial growth. This method permits the liquid phase epitaxial growth of a semiconductor layer even on an Al.sub.x Ga.sub.1.sub.-x As (x .gtoreq. 0.3) which is once exposed to the air or subjected to an etching treatment. Accordingly, this method is suitable for the manufacture of a semiconductor element having a buried active layer. This method also permits the manufacture of an epitaxial wafer having a low dislocation density.
    Type: Grant
    Filed: June 26, 1975
    Date of Patent: June 21, 1977
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Yoshiji Horikoshi, Yoshitaka Furukawa