Patents by Inventor Yoshitaka Hirai

Yoshitaka Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7394319
    Abstract: A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 1, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Yoshitaka Hirai
  • Publication number: 20060255866
    Abstract: A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoshitaka Hirai
  • Publication number: 20060115126
    Abstract: An ECU of a night vision system stores small obtained images of provisional targets as six templates depending on the distance from infrared cameras, and selects one of the templates depending on the distance up to an actual object. Using the selected template, the ECU performs template matching on images obtained by the infrared cameras, and calculates coordinates of the inspection target. The ECU compares the calculated coordinates of the inspection target and stored reference coordinates with each other, and determines mounted angles of the infrared cameras.
    Type: Application
    Filed: November 23, 2005
    Publication date: June 1, 2006
    Applicant: Honda Motor Co., Ltd.
    Inventors: Masahito Watanabe, Masakazu Saka, Nobuharu Nagaoka, Yoshitaka Hirai, Toshiya Okabe
  • Publication number: 20050215656
    Abstract: A photocurable and thermosetting composition comprises (A) a carboxyl group-containing resin having at least one carboxyl group in its molecule, (B) a photopolymerization initiator having an oxime linkage represented by the following general formula (I), (C) a reactive diluent, and (D) an epoxy compound having two or more epoxy groups in its molecule. The above-mentioned photopolymerization initiator (B) is incorporated into a formulation which is different from at least a formulation into which the above-mentioned carboxyl group-containing resin (A) and the above-mentioned reactive diluent (C) are incorporated to formulate a system comprising at least two parts.
    Type: Application
    Filed: May 26, 2005
    Publication date: September 29, 2005
    Inventors: Hideaki Kojima, Hidekazu Miyabe, Shouji Minegishi, Naoki Yoneda, Yoshitaka Hirai
  • Patent number: 6794944
    Abstract: There is provided a lock detection circuit for optimizing a lock detection time and an unlock detection time of a PLL circuit. The present invention has counters 21 and 22 for inputting and counting feedback signals and reference signals inputted to a phase comparator 11 of a PLL circuit 10; a comparison circuit 23 for inputting and comparing count values of the counters 21 and 22 and outputting a control signal in an active state when the count value of the counter 21 is a first value and the count value of the counter 22 is the first value; a counter 24 for counting the feedback signals when the control signal outputted from the comparison circuit 23 is active; and a decision circuit 25 for outputting an output signal of a value showing a lock state when a count value of the counter 24 reaches a second value. The comparison circuit 23 resets the counter 24 when the count value of the counter 21 is the first value and the count value of the counter 22 is not the first value.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: September 21, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Yoshitaka Hirai
  • Publication number: 20020180540
    Abstract: There is provided a lock detection circuit for optimizing a lock detection time and an unlock detection time of a PLL circuit. The present invention has counters 21 and 22 for inputting and counting feedback signals and reference signals inputted to a phase comparator 11 of a PLL circuit 10; a comparison circuit 23 for inputting and comparing count values of the counters 21 and 22 and outputting a control signal in an active state when the count value of the counter 21 is a first value and the count value of the counter 22 is the first value; a counter 24 for counting the feedback signals when the control signal outputted from the comparison circuit 23 is active; and a decision circuit 25 for outputting an output signal of a value showing a lock state when a count value of the counter 24 reaches a second value. The comparison circuit 23 resets the counter 24 when the count value of the counter 21 is the first value and the count value of the counter 22 is not the first value.
    Type: Application
    Filed: April 9, 2002
    Publication date: December 5, 2002
    Inventor: Yoshitaka Hirai