Abstract: According to one embodiment, an automatic analyzer includes: a plurality of reaction tube holders each configured to hold a reaction tube housing a mixed solution of a specimen and a reagent; a plurality of photometry portions respectively provided with respect to the reaction tube holders and each configured to perform photometry on the mixed solution housed in the reaction tube; a reaction bath including the reaction tube holders and the photometry portions and configured to repeat rotating and stopping to thereby convey the reaction tube held by each of the reaction tube holders; and a driver configured to rotate the reaction bath.

Abstract: An automatic analyzing apparatus according to the present embodiment includes a specimen container, a piercer, a detector, and processing circuitry. The specimen container is a container in which a specimen is housed, an opening of the specimen container being sealed by a cap. The piercer pierces the cap by a distal end. The detector detects a blot on the cap. The processing circuitry controls a piercing operation of the piercer.

Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract: A delay library generation apparatus, associated control method, and associated program are provided. The delay library generation apparatus comprises a storage device which stores architecture information of a logic element array, layout data of an overall programmable logic device, a netlist of the overall programmable logic device, and a wiring route extraction unit which refers to the storage device and extracts wiring route information regarding a wiring route section based on the architecture information. Moreover, the delay library generation apparatus comprises an analyzing unit which analyzes the layout data of the logic device and extracts parameters of a parasitic element and a crosstalk between adjacent interconnections. The delay generation apparatus further comprises a delay calculation unit which calculates delay data based on the extracted parameters and a delay library generation unit which generates a delay library of the logic device based on the wiring route information and the delay data.

Abstract: A delay library generation apparatus (1) includes: a storage device (30) which stores architecture information (31) of a logic element array, layout data (35) of an overall programmable logic device, and a netlist (39) of the overall programmable logic device; a wiring route extraction unit (21) which refers to the storage device (30), and extracts wiring route information (33) regarding a wiring route section, based on the architecture information (31); an analyzing unit (23) which analyzes the layout data (35) of the overall programmable logic device, and extracts parameters of a parasitic element and a crosstalk caused between adjacent interconnections, the parasitic element and said crosstalk caused due to said global interconnection; a delay calculation unit (25) which calculates detailed delay data (37) based on the extracted parameters; and a delay library generation unit (27) which generates a delay library (41) of the programmable logic device, based on the wiring route information (33) and the detai

Abstract: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.

Abstract: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.