Patents by Inventor Yoshitaka Kamo
Yoshitaka Kamo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11374134Abstract: Examples of an electronic component device includes a housing formed of a member that causes radiation to lose its energy by generating an electric charge when the housing is subjected to the radiation and an electronic component housed in the housing. The member is a semiconductor device member having a PN junction.Type: GrantFiled: February 28, 2018Date of Patent: June 28, 2022Assignee: Mitsubishi Electric CorporationInventor: Yoshitaka Kamo
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Patent number: 11283415Abstract: A MIM capacitor is included in any one or more of a first matching circuit and a second matching circuit. The mat capacitor performs impedance matching of a fundamental wave included in a high-frequency signal with a transmission line, and forms a short-circuit point for a harmonic included in the high-frequency signal at a connection point with the transmission line.Type: GrantFiled: July 14, 2017Date of Patent: March 22, 2022Assignee: Mitsubishi Electric CorporationInventors: Dai Ninomiya, Eigo Kuwata, Kazuhiko Nakahara, Makoto Kimura, Yoshitaka Kamo
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Publication number: 20210328557Abstract: A MIM capacitor is included in any one or more of a first matching circuit and a second matching circuit. The mat capacitor performs impedance matching of a fundamental wave included in a high-frequency signal with a transmission line, and forms a short-circuit point for a harmonic included in the high-frequency signal at a connection point with the transmission line.Type: ApplicationFiled: July 14, 2017Publication date: October 21, 2021Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Dai NINOMIYA, Eigo KUWATA, Kazuhiko NAKAHARA, Makoto KIMURA, Yoshitaka KAMO
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Publication number: 20200373441Abstract: Examples of an electronic component device includes a housing formed of a member that causes radiation to lose its energy by generating an electric charge when the housing is subjected to the radiation and an electronic component housed in the housing. The member is a semiconductor device member having a PN junction.Type: ApplicationFiled: February 28, 2018Publication date: November 26, 2020Applicant: Mitsubishi Electric CorporationInventor: Yoshitaka KAMO
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Publication number: 20170294887Abstract: A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.Type: ApplicationFiled: November 25, 2016Publication date: October 12, 2017Applicant: Mitsubishi Electric CorporationInventors: Yoshitaka KAMO, Yoshitsugu YAMAMOTO
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Patent number: 9647615Abstract: Parallel capacitors (5c and 5d) of impedance matching circuits (5) which are connected to two transistors (1), respectively, have their first ends connected to a ground through via holes (5e and 5f) that are used in common, respectively. Although a conventional circuit necessitates via holes by the number equal to the number of stages multiplied by the number of cells of the transistors (1) for an LPF type impedance matching circuit (3), the present circuit can halve the number of via holes of the LPF type impedance matching circuit (5), thereby being able to downsize the circuit.Type: GrantFiled: November 26, 2013Date of Patent: May 9, 2017Assignee: Mitsubishi Electric CorporationInventors: Eigo Kuwata, Koji Yamanaka, Hiroshi Otsuka, Tasuku Kirikoshi, Yoshitaka Kamo
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Patent number: 9640647Abstract: A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of SiN; and a second insulating film covering the schottky electrode and the first insulating film and formed of AlO whose atomic layers are alternately disposed.Type: GrantFiled: May 3, 2016Date of Patent: May 2, 2017Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Okazaki, Kenichiro Kurahashi, Hidetoshi Koyama, Toshiaki Kitano, Yoshitaka Kamo
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Publication number: 20170077275Abstract: A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of SiN; and a second insulating film covering the schottky electrode and the first insulating film and formed of AlO whose atomic layers are alternately disposed.Type: ApplicationFiled: May 3, 2016Publication date: March 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki OKAZAKI, Kenichiro KURAHASHI, Hidetoshi KOYAMA, Toshiaki KITANO, Yoshitaka KAMO
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Publication number: 20160099690Abstract: The connection intervals of N amplifier blocks 3-1 to 3-N to an input transmission line 1 increase with the distance from a signal input terminal RFin, and among the N amplifier blocks 3-1 to 3-N, the input capacitor 4 in an amplifier block 3-n connected to the input transmission line 1 at a more distant side from the signal input terminal RFin has a lower capacitance value Cn.Type: ApplicationFiled: April 4, 2014Publication date: April 7, 2016Applicant: Mitsubshi Electric CorporationInventors: Eigo KUWATA, Koji YAMANAKA, Tasuku KIRIKOSHI, Yoshitaka KAMO
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Patent number: 9117896Abstract: A semiconductor device includes: a Si substrate having first and second major surfaces facing in opposite directions; a buffer layer of AlxGa1-xN (0?x?1) on the first major surface of the Si substrate; an epitaxially grown crystalline layer of AlyGa1-yN (0?y?1, x?y) on the buffer layer; a transistor on the epitaxially grown crystalline layer; and a filler of AlxGa1-xN and having the same x as the buffer layer. A through hole in the Si substrate extends from the second major surface to the buffer layer, and the through hole is filled with the filler.Type: GrantFiled: June 4, 2014Date of Patent: August 25, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroyuki Okazaki, Yoshitaka Kamo, Yoichi Nogami, Hidetoshi Koyama, Shinichi Miyakuni
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Publication number: 20150229283Abstract: Parallel capacitors (5c and 5d) of impedance matching circuits (5) which are connected to two transistors (1), respectively, have their first ends connected to a ground through via holes (5e and 5f) that are used in common, respectively. Although a conventional circuit necessitates via holes by the number equal to the number of stages multiplied by the number of cells of the transistors (1) for an LPF type impedance matching circuit (3), the present circuit can halve the number of via holes of the LPF type impedance matching circuit (5), thereby being able to downsize the circuit.Type: ApplicationFiled: November 26, 2013Publication date: August 13, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Eigo Kuwata, Koji Yamanaka, Hiroshi Otsuka, Tasuku Kirikoshi, Yoshitaka Kamo
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Publication number: 20150084103Abstract: A semiconductor device includes: a Si substrate having first and second major surfaces facing in opposite directions; a buffer layer of AlxGa1-xN (0?x?1) on the first major surface of the Si substrate; an epitaxially grown crystalline layer of AlyGa1-yN (0?y?1, x?y) on the buffer layer; a transistor on the epitaxially grown crystalline layer; and a filler of AlxGa1-xN and having the same x as the buffer layer. A through hole in the Si substrate extends from the second major surface to the buffer layer, and the through hole is filled with the filler.Type: ApplicationFiled: June 4, 2014Publication date: March 26, 2015Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki Okazaki, Yoshitaka Kamo, Yoichi Nogami, Hidetoshi Koyama, Shinichi Miyakuni
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Patent number: 8912099Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: GrantFiled: July 30, 2013Date of Patent: December 16, 2014Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Patent number: 8809989Abstract: A semiconductor device includes: a semiconductor substrate having a hexagonal crystalline structure with a c-axis and c-planes; and transistors on a c plane of the semiconductor substrate. Source electrodes of the transistors are connected to each other. Drain electrodes of the transistors are connected to each other. Gate electrodes of the transistors are connected to each other. The gate electrodes of the transistors extend along directions that form angles with each other that are 60 degrees or 120 degrees, in a plan view seen from a direction perpendicular to the c plane of the semiconductor substrate.Type: GrantFiled: March 18, 2013Date of Patent: August 19, 2014Assignee: Mitsubishi Electric CorporationInventor: Yoshitaka Kamo
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Patent number: 8778748Abstract: A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.Type: GrantFiled: January 23, 2012Date of Patent: July 15, 2014Assignee: Mitsubishi Electric CorporationInventor: Yoshitaka Kamo
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Publication number: 20140134835Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: ApplicationFiled: July 30, 2013Publication date: May 15, 2014Applicant: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Publication number: 20140008728Abstract: A semiconductor device includes: a semiconductor substrate having a hexagonal crystalline structure with a c-axis and c-planes; and transistors on a c plane of the semiconductor substrate. Source electrodes of the transistors are connected to each other. Drain electrodes of the transistors are connected to each other. Gate electrodes of the transistors are connected to each other. The gate electrodes of the transistors extend along directions that form angles with each other that are 60 degrees or 120 degrees, in a plan view seen from a direction perpendicular to the c plane of the semiconductor substrate.Type: ApplicationFiled: March 18, 2013Publication date: January 9, 2014Applicant: Mitsubishi Electric CorporationInventor: Yoshitaka Kamo
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Publication number: 20120315708Abstract: A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.Type: ApplicationFiled: January 23, 2012Publication date: December 13, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Yoshitaka KAMO
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Patent number: 8008667Abstract: A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements.Type: GrantFiled: December 13, 2007Date of Patent: August 30, 2011Assignee: Mitsubishi Electric CorporationInventors: Hidetoshi Koyama, Yoshitaka Kamo
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Patent number: 7851831Abstract: A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. A first portion of the gate electrode layer, in contact with the nitride semiconductor layer, has a higher nitrogen mole fraction than a second portion of the gate electrode layer.Type: GrantFiled: September 24, 2007Date of Patent: December 14, 2010Assignee: Mitsubishi Electric CorporationInventors: Hidetoshi Koyama, Yoshitaka Kamo, Toshihiko Shiga