Patents by Inventor Yoshitaka Katoh

Yoshitaka Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Assisting in logic circuit design to place cells on an IC substrate and optimize wiring
    Patent number: 8904327
    Abstract: A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when the logic circuit has multiple levels, to provide a device assisting in the design of a logic circuit using this method, and to provide a computer program executable by this device. The cells of all levels are placed in a placement area formed on a grid, and a port enabling connection to a cell in another level is placed in a boundary portion between the placement area having cells already placed and a placement area enabling placement of new cells. Cells in the same level are wired between cells and cells in another level are wired between a cell and a port so that the sum total of the wiring lengths may be minimized.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventor: Yoshitaka Katoh
  • Method For Assisting in Logic Circuit Design to Place Cells on IC Substrate and Optimize Wiring, Device For Assisting in Logic Circuit Design Using This Method, and Computer Program Executable By This Device
    Publication number: 20140033153
    Abstract: A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when the logic circuit has multiple levels, to provide a device assisting in the design of a logic circuit using this method, and to provide a computer program executable by this device. The cells of all levels are placed in a placement area formed on a grid, and a port enabling connection to a cell in another level is placed in a boundary portion between the placement area having cells already placed and a placement area enabling placement of new cells. Cells in the same level are wired between cells and cells in another level are wired between a cell and a port so that the sum total of the wiring lengths may be minimized.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Yoshitaka Katoh