Abstract: A navigation device and the like capable of appropriately alleviating an amount of communicating information between the navigation server and a navigation device, from the viewpoint of guiding a user to a destination point via the navigation device, on the basis of a support route which is set by the navigation server. Of the links constituting a support route R which connects the current position p1 and the destination position p2 of the user, the links satisfying an extraction condition set according to a changing pattern of a road type are extracted as target links. Also, the target links, that is, the link having high necessity from the viewpoint of guiding the user, with regard to the changing pattern of the road type, is recognized by the navigation device 200 on the basis of communication between the navigation server 100 and the navigation device 200.

Abstract: The present invention is directed to the provision of a liquid crystal panel that can solve the problem that bubbles are formed in a liquid crystal layer. More specifically, the invention provides a liquid crystal panel includes a first plastic substrate; a second plastic substrate, a liquid crystal layer sealed between the first and second plastic substrates, a transparent conductive layer provided on the first or the second plastic substrate and having a patterned region for driving the liquid crystal layer, and an opening provided in the patterned region of the transparent conductive layer.

Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1-x-yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).

Abstract: A semiconductor light emitting device includes a substrate 11 including a group III-V nitride semiconductor; a first-conductivity-type layer 12 formed on the substrate 11, the first-conductivity-type layer including a plurality of group III-V nitride semiconductor layers of first conductivity type; an active layer 13 formed on the first semiconductor layer 12; and a second-conductivity-type layer 14 formed on the active layer 13, the second-conductivity-type layer including a group III-V nitride semiconductor layer of second conductivity type. The first-conductivity-type layer 12 includes an intermediate layer 23 made of Ga1-nInxN (0<x<1).

Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1?x?yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).

Abstract: A semiconductor light emitting element includes a substrate 11 having a defect concentrated region 11a which has a crystal defect density higher than in the other region. On the substrate 11, a semiconductor layer 12 is formed. On the defect concentrated region 11a, a first electrode 13 is formed. On the semiconductor layer 12, a second electrode 14 is formed.

Abstract: A plurality of semiconductor layers including a light-emitting layer (14) are formed on the main surface of a substrate (10) which is composed of a group III-V nitride semiconductor. A first n-type semiconductor layer (12) containing indium is formed between the light-emitting layer (14) and the substrate (10), thereby reducing the affect of damage in the substrate surface. By having such a structure, there is realized a semiconductor light-emitting device having uniform characteristics.

Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1?x?yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

Abstract: A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.

Abstract: An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.

Abstract: Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Abstract: Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Abstract: According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.