Patents by Inventor Yoshitaka Kyogoku

Yoshitaka Kyogoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8058565
    Abstract: In a semiconductor device (1), a package board (2) is provided in which a plurality of wiring layers are layered, a plurality of mounting pads (5) arranged in a matrix are provided to the uppermost wiring layer of the package board (2), and solder bumps (7) are connected to the mounting pads (5). A semiconductor chip (9) is mounted on the package board (2) via the solder bumps (7). The uppermost wiring layer of the package board (2) is formed from a resin material in which the Young's modulus is 1 GPa or lower when the temperature is 10 to 30° C., and the elongation at break is 50% or higher.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: November 15, 2011
    Assignee: NEC Corporation
    Inventors: Yukihiro Kiuchi, Masahiro Ishibashi, Yoshitaka Kyogoku
  • Patent number: 7981963
    Abstract: In a semiconductor device, the topmost wiring layer of the package board is formed from an insulation material in which the elongation at break is 20% or higher and Young's modulus is 1 GPa or less when the temperature is 10 to 30° C. This insulation material contains a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent; an epoxy resin; an epoxy resin curing agent; and a crosslinked styrene-butadiene rubber having a double bond and a hydroxyl group, a carboxylic group, or another polar group. It is therefore possible to provide a semiconductor device that has a wiring board in which the connection reliability in relation to temperature cycles is high and the adhesiveness between the insulation layer and the electroless copper plating layer is also high.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: July 19, 2011
    Assignee: NEC Corporation
    Inventors: Yukihiro Kiuchi, Masahiro Ishibashi, Yoshitaka Kyogoku, Masatoshi Iji
  • Publication number: 20070274060
    Abstract: In a semiconductor device (1), a package board (2) is provided in which a plurality of wiring layers are layered, a plurality of mounting pads (5) arranged in a matrix are provided to the uppermost wiring layer of the package board (2), and solder bumps (7) are connected to the mounting pads (5). A semiconductor chip (9) is mounted on the package board (2) via the solder bumps (7). The uppermost wiring layer of the package board (2) is formed from a resin material in which the Young's modulus is 1 GPa or lower when the temperature is 10 to 30° C., and the elongation at break is 50% or higher.
    Type: Application
    Filed: April 15, 2005
    Publication date: November 29, 2007
    Inventors: Yukihiro Kiuchi, Masahiro Ishibashi, Yoshitaka Kyogoku
  • Publication number: 20070251721
    Abstract: In a semiconductor device, the topmost wiring layer of the package board is formed from an insulation material in which the elongation at break is 20% or higher and Young's modulus is 1 GPa or less when the temperature is 10 to 30° C. This insulation material contains a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent; an epoxy resin; an epoxy resin curing agent; and a crosslinked styrene-butadiene rubber having a double bond and a hydroxyl group, a carboxylic group, or another polar group. It is therefore possible to provide a semiconductor device that has a wiring board in which the connection reliability in relation to temperature cycles is high and the adhesiveness between the insulation layer and the electroless copper plating layer is also high.
    Type: Application
    Filed: April 10, 2007
    Publication date: November 1, 2007
    Applicant: NEC CORPORATION
    Inventors: Yukihiro Kiuchi, Masahiro Ishibashi, Yoshitaka Kyogoku, Masatoshi Iji