Patents by Inventor Yoshitaka Kyougoku

Yoshitaka Kyougoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378032
    Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.
    Type: Application
    Filed: February 28, 2023
    Publication date: November 23, 2023
    Inventors: Kosuke KITAICHI, Masatoshi SUGIURA, Hideaki TAMIMOTO, Takehiko MAEDA, Keita TAKADA, Yoshitaka KYOUGOKU
  • Publication number: 20180090451
    Abstract: While strength of a wiring board in a semiconductor substrate is ensured, thermal conductivity is increased. A BGA includes a wiring board having an upper surface and a lower surface, a semiconductor chip mounted on the upper surface of the wiring board, and ball electrodes that are a plurality of external terminals provided on the lower surface of the wiring board. The wiring board includes an insulation layer arranged between wiring layers. The insulation layer includes a resin layer, another resin layer, and an electrically conducting layer arranged between the resin layer and the other resin layer. The electrically conducting layer is formed by a lamination of a graphite sheet and a metal layer.
    Type: Application
    Filed: July 20, 2017
    Publication date: March 29, 2018
    Inventors: Yoshihisa MATSUBARA, Yasuhiro SHIMADA, Yoshitaka KYOUGOKU
  • Patent number: 8304905
    Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Matsui, Tsuyoshi Eda, Akira Matsumoto, Yoshitaka Kyougoku, Shinji Watanabe, Hirokazu Honda
  • Publication number: 20120025371
    Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi MATSUI, Tsuyoshi EDA, Akira MATSUMOTO, Yoshitaka KYOUGOKU, Shinji WATANABE, Hirokazu HONDA
  • Publication number: 20030121698
    Abstract: A printed wiring board includes an insulating layer, and an electrode pad and interconnect that is connected to the electrode pad that are provided on the insulating layer. A vacant space is formed in the insulating layer, and of the electrode pad and interconnect, at least a portion of the electrode pad is exposed in the vacant space.
    Type: Application
    Filed: December 13, 2002
    Publication date: July 3, 2003
    Applicant: NEC CORPORATION
    Inventors: Yoshitaka Kyougoku, Masahiro Ishibashi
  • Patent number: 6287892
    Abstract: A plurality of substrate to which have been flip-chip mounted semiconductor chips are laminated by solder bumps provided for the purpose of lamination. A elastic resin is caused to fill the space between the chip upper surface and the substrate, thus providing a shock-absorbing material layer.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventors: Nobuaki Takahashi, Yoshitaka Kyougoku, Katsumasa Hashimoto, Shinichi Miyazaki
  • Patent number: 6025648
    Abstract: A plurality of substrates 1 to which have been flip-chip mounted semiconductor chips 2 are laminated by means of solder bumps 7 provided for the purpose of lamination. A elastic resin is caused to fill the space between the chip upper surface 9 and the substrate 1, thus providing a shock-absorbing material layer 8. By adopting this type of three-dimensional semiconductor modular structure, the shock-absorbing material layer 8 absorbs externally applied vibration and shock, thereby improving the immunity to vibration and shock.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: February 15, 2000
    Assignee: NEC Corporation
    Inventors: Nobuaki Takahashi, Yoshitaka Kyougoku, Katsumasa Hashimoto, Shinichi Miyazaki
  • Patent number: 5995379
    Abstract: Substrates 1, 2 include chip select electrode pads B1, B2, C1, C2, and first chip select electrode pads B1, C1 are connected to chip select terminals of semiconductor chips 3, 4. The other chip select electrodes B2, C2 are connected to opposite surface side electrodes B1', C1' positioned on the opposite surface side of the chip select electrodes B1, C1 adjacent in the direction of the first chip select electrodes. The opposite surface side electrode B1 and the chip select electrode C1 of the substrate confronted therewith are connected to each other by a conductive bump 6. Thus, the substrates 1, 2 have the same structure.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventors: Yoshitaka Kyougoku, Kazuhiko Ohkubo