Abstract: A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.

Abstract: A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.

Abstract: A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a current consumption control circuit including a switch transistor and a resistor. In this case, the amount of electric current which the nonvolatile memory consumes and the amount of electric current which the resistor consumes are substantially the same. When the nonvolatile memory is in a non-operation state, the current consumption control circuit turns ON the switch transistor by a memory activation signal and consumes substantially the same amount of electric current as the amount of electric current which the nonvolatile memory consumes. When the nonvolatile memory is in an operation state, the current consumption control circuit turns OFF the switch transistor and stops electric current consumption by the resistor.

Abstract: A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a current consumption control circuit including a switch transistor and a resistor. In this case, the amount of electric current which the nonvolatile memory consumes and the amount of electric current which the resistor consumes are substantially the same. When the nonvolatile memory is in a non-operation state, the current consumption control circuit turns ON the switch transistor by a memory activation signal and consumes substantially the same amount of electric current as the amount of electric current which the nonvolatile memory consumes. When the nonvolatile memory is in an operation state, the current consumption control circuit turns OFF the switch transistor and stops electric current consumption by the resistor.

Abstract: In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit 4 is provided with a reference potential generation circuit 1, a divided voltage potential generation circuit 2 and a differential amplification circuit 3 for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory 5 which stores correction data for correcting the reference potential, a data latch circuit 7 for storing correction data that has been read out, and a microcomputer logic unit 6 for controlling ferroelectric memory 5 as well as data latch circuit 7 are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.

Abstract: In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit 4 is provided with a reference potential generation circuit 1, a divided voltage potential generation circuit 2 and a differential amplification circuit 3 for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory 5 which stores correction data for correcting the reference potential, a data latch circuit 7 for storing correction data that has been read out, and a microcomputer logic unit 6 for controlling ferroelectric memory 5 as well as data latch circuit 7 are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.

Abstract: To provide a ferroelectric memory, in which data can be positively protected even in an event of fluctuations in process parameter, time can be shortened for a reliability estimation test, and it is possible to avoid device breakage resulted from the test. A source voltage VDD is detected by using a source voltage detection circuit having a stable detection level. When a detected voltage RREFA is at or lower than a set detection level VREFA, an external input terminal XEXTCE is deactivated by using an output signal of a differential amplifier circuit to protect data. Thus, it is possible to protect data with stability.

Abstract: To provide a ferroelectric memory, in which data can be positively protected even in an event of fluctuations in process parameter, time can be shortened for a reliability estimation test, and it is possible to avoid device breakage resulted from the test. A source voltage VDD is detected by using a source voltage detection circuit having a stable detection level. When a detected voltage RREFA is at or lower than a set detection level VREFA, an external input terminal XEXTCE,is deactivated by using an output signal of a differential amplifier circuit to protect data. Thus, it is possible to protect data with stability.

Abstract: In a dynamic random access memory (DRAM), first and second output transistors form an NMOS-type tristate output buffer. Interposed between a gate electrode of the first output transistor and a data input/output terminal (DQ terminal) is an auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the first output transistor. Further interposed between the DQ terminal and a gate electrode of the second output transistor is another auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the second output transistor. Both auxiliary transistors lower gate voltages of both output transistors down to a negative voltage level such that both output transistors are maintained as cut off when a negative voltage is externally applied to the DQ terminal at the time of high impedance.

Abstract: In a semiconductor memory device having word-line-resetting ability regulating transistors each placed between the corresponding one of a large number of word lines and the ground, each of the above word-line-resetting-ability regulating transistors is composed of first and second transistors connected in series. During standby, the gate voltage of the above second transistor is controlled to be at a set low value (e.g., a value of about 1 V, which is higher than the threshold voltage of the above resetting-ability regulating transistors by 0.2 to 0.5 V). During the operation of the semiconductor memory device, the gate voltage of the second transistor is controlled to be at a value (e.g., 3.3 V) lower than a value of a power source for row decoders (e.g., 5 V) and higher than the above set low value when the corresponding word line is selected, while it is controlled to be at the above set low value (1 V) when the corresponding word line is not selected.