Patents by Inventor Yoshitaka Ochiai
Yoshitaka Ochiai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130284304Abstract: In the present spinning method using elements including: a tube material; a pair of chucks which hold both ends of the tube material; and a roller having a predetermined curved shape in order to shape the tube material, in a state that circumferential portions at the both ends of the tube material are fitted in and held by circumferential grooves provided on side surfaces of the chucks, the method includes a step of transferring a curved shape on a side surface of the roller to a side surface of the tube material by rotating the chucks which hold the tube material around a first axis, rotating the roller around a second axis, moving the rotating roller in an X direction, and pressing the side surface of the roller against the side surface of the tube material between the rotating chucks.Type: ApplicationFiled: April 25, 2013Publication date: October 31, 2013Applicant: HITACHI, LTD.Inventors: YounJeong HONG, Toshimi SATO, Kenichirou HIRANO, Takahiro MAKIYAMA, Toshiya TERAMAE, Yoshitaka OCHIAI
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Patent number: 7508068Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.Type: GrantFiled: February 1, 2007Date of Patent: March 24, 2009Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20070159864Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.Type: ApplicationFiled: February 1, 2007Publication date: July 12, 2007Applicants: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Patent number: 7193317Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.Type: GrantFiled: July 2, 2003Date of Patent: March 20, 2007Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Patent number: 6943445Abstract: The present invention provides a semiconductor device which reduces an inductance of wiring for bridge-connecting semiconductor switches and realizes a reduction in size. Within the semiconductor device formed are two controllable bridge-connected semiconductor switches 13a and 13b, an output terminal, positive/negative polarity DC terminals 2 and 3, and an insulating substrate 15a in which conductor layers 12, 17 and 19 having a conductor section and in an inner layer for bridge-connecting the semiconductor switches to the DC terminals on a surface thereof and insulating layers 16 and 18 are alternately laminated. The surface and inner-layer conductor layers 12 and 17 which interpose the insulating layer 16 therebetween are electrically connected by a conductor 20 passing through the insulating layer 16 interposed between the conductor layers 12 and 17.Type: GrantFiled: March 29, 2002Date of Patent: September 13, 2005Assignee: Hitachi, Ltd.Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Shinichi Fujino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20050147839Abstract: In order to solve the issue mentioned above, the present invention is featured in electrically conductive adhesive sheet: wherein the substrate 1 which composes electrically, thermally, or electrically and thermally conducting paths in a direction along the plane of the sheet is formed of metallic foil having a coefficient of thermal expansion between the coefficient of thermal expansion of one of at least two bonded members and the coefficient of thermal expansion of another one of the bonded members. In accordance with the present invention adopting the composition mentioned above, a stress applied to the protrusion layer 2, which composes electrically, thermally, or both electrically and thermally conducting paths between the substrate 1 and the bonded members by difference in thermal expansion, can be moderated.Type: ApplicationFiled: January 5, 2005Publication date: July 7, 2005Inventors: Tokihito Suwa, Satoru Shigeta, Shinji Shirakawa, Yoshitaka Ochiai
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Patent number: 6873045Abstract: One method of achieving the above subjects is by connecting one of electroconductive members 12, which are pre-connected to the top and bottom of a semiconductor chip 11 and have thermal conductivity, to an electroconductive member 13, which is used with the semiconductor chip 11 to constitute a laminated structure, in electrically insulated form on the same surface as the installation surface of the electroconductive member 13 so as to straddle the laminated structure constituted by the semiconductor chip 11 and the electroconductive member 13.Type: GrantFiled: July 2, 2003Date of Patent: March 29, 2005Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Patent number: 6843335Abstract: A positive side conductor and a negative side conductor of an input terminal electrically connected to semiconductor elements, are electrically insulated from each other, and are laminated with each other, and the input terminal having such a laminated structure, an output terminal and substrates mounted thereon the semiconductor elements are arranged in a checkered pattern in a container. Further, the semiconductor elements mounted on the substrates, the input terminal and the output terminal are electrically connected to one another so as to obtain a loop-like electric path on a conductive member, thereby it is possible to aim at miniaturizing the power conversion apparatus and lowering the inductance thereof.Type: GrantFiled: December 21, 2001Date of Patent: January 18, 2005Assignee: Hitachi, Ltd.Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Shinichi Fujino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20040113268Abstract: The present invention provides a semiconductor device which reduces an inductance of wiring for bridge-connecting semiconductor switches and realizes a reduction in size. Within the semiconductor device formed are two controllable bridge-connected semiconductor switches 13a and 13b, an output terminal, positive/negative polarity DC terminals 2 and 3, and an insulating substrate 15a in which conductor layers 12, 17 and 19 having a conductor section and in an inner layer for bridge-connecting the semiconductor switches to the DC terminals on a surface thereof and insulating layers 16 and 18 are alternately laminated. The surface and inner-layer conductor layers 12 and 17 which interpose the insulating layer 16 therebetween are electrically connected by a conductor 20 passing through the insulating layer 16 interposed between the conductor layers 12 and 17.Type: ApplicationFiled: August 14, 2003Publication date: June 17, 2004Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Shinichi Fujino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20040104446Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.Type: ApplicationFiled: July 2, 2003Publication date: June 3, 2004Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20040012064Abstract: One method of achieving the above subjects is by connecting one of electroconductive members 12, which are pre-connected to the top and bottom of a semiconductor chip 11 and have thermal conductivity, to an electroconductive member 13, which is used with the semiconductor chip 11 to constitute a laminated structure, in electrically insulated form on the same surface as the installation surface of the electroconductive member 13 so as to straddle the laminated structure constituted by the semiconductor chip 11 and the electroconductive member 13.Type: ApplicationFiled: July 2, 2003Publication date: January 22, 2004Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20020195286Abstract: A positive side conductor and a negative side conductor of an input terminal electrically connected to semiconductor elements, are electrically insulated from each other, and are laminated with each other, and the input terminal having such a laminated structure, an output terminal and substrates mounted thereon the semiconductor elements are arranged in a checkered pattern in a container. Further, the semiconductor elements mounted on the substrates, the input terminal and the output terminal are electrically connected to one another so as to obtain a loop-like electric path on a conductive member, thereby it is possible to aim at miniaturizing the power conversion apparatus and lowering the inductance thereof.Type: ApplicationFiled: December 21, 2001Publication date: December 26, 2002Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Shinichi Fujino, Hiromichi Anan, Yoshitaka Ochiai
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Publication number: 20020180037Abstract: A semiconductor device including a positive polarity wiring plate, negative wiring plate, more than one output wiring plate, semiconductor switch element and conductive buffer or “cushion” member is disclosed. The semiconductor switch element and cushion member are compressively interposed between the output wiring plate and positive wiring plate and also between the output wiring plate and negative wiring plate to thereby constitute bridge circuitry. The positive wiring plate, negative wiring plate or output wiring plate is for use as one support body of a pressurization structure. With such an arrangement, it is possible to improve the heat releasability of semiconductor elements while at the same time reducing the inductance of direct current (DC) circuitry to thereby suppress heat generation of the semiconductor elements, thus increasing the reliability relative to temperature cycles.Type: ApplicationFiled: September 7, 2001Publication date: December 5, 2002Applicant: Hitachi, Ltd.Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Hiromichi Anan, Yoshitaka Ochiai
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Patent number: 5958575Abstract: A magneto-optical recording medium is disclosed in which magnetic layer has a multi-layer structure consisting of an artificial lattice film constituted by a Co layer and a Pt layer and/or a Pd layer stacked together and a rare earth-transition metal layer. High coercivity may be achieved by the rare earth-transition metal film whilst a satisfactory Kerr rotation angle in the short wavelength range may be assured by the artificial lattice film. The magneto-optical recording medium may cope with the next-generation high density recording employing a short wavelength laser.Type: GrantFiled: October 26, 1995Date of Patent: September 28, 1999Assignee: Sony CorporationInventors: Kensuke Fijimoto, Shunichi Hashimoto, Yoshitaka Ochiai
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Patent number: 5400307Abstract: A magneto-optical recording medium is disclosed in which a magneto-optical recording layer is formed by alternately stacking Co layers and Pt and/or Pd layers, and having a total thickness between 50 and 800 .ANG..Type: GrantFiled: June 22, 1994Date of Patent: March 21, 1995Assignee: Sony CorporationInventors: Yoshitaka Ochiai, Shunichi Hashimoto, Koichi Aso
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Patent number: 5296989Abstract: A magnetic head comprising a magnetic path and a vertically magnetizable film. The magnetic path contains a first gap facing a magnetic recording medium and a second gap. The vertically magnetizable film is formed across the second gap on the principal plane or outer circumference of the magnetic path. A linearly polarized light beam is irradiated onto the vertically magnetizable film and the resulting reversal of magnetization in the vertically magnetizable film is detected through the use of a polar Kerr effect. This scheme allows data to be reproduced with sufficient sensitivity from tracks of very small widths.Type: GrantFiled: July 23, 1993Date of Patent: March 22, 1994Assignee: Sony CorporationInventors: Yoshitaka Ochiai, Hideki Matsuda, Takehiro Nagaki, Shunichi Hashimoto
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Patent number: 4748000Abstract: Disclosed is a soft magnetic thin film which has superior soft magnetic characteristics and high saturation magnetic flux density. The magnetic thin film is formed by physical vapor deposition process and composed of Fe, Ga, and Si with optional inclusion of Co, Ru, or Cr.Type: GrantFiled: April 10, 1986Date of Patent: May 31, 1988Assignee: Sony CorporationInventors: Kazuhiko Hayashi, Masatoshi Hayakawa, Yoshitaka Ochiai, Hideki Matsuda, Wataru Ishikawa, You Iwasaki, Kouichi Aso
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Patent number: 4707417Abstract: A magnetic alloy thin film consisting essentially of a first Fe-Al-Si or Fe-Ni alloy thin film of high permeability and a second Fe-Si alloy thin film directly formed on the first thin film and having high saturation magnetic flux density. The ratio in thickness of the first and second films is preferably in the range of from 1:0.1 to 2.Type: GrantFiled: July 16, 1985Date of Patent: November 17, 1987Assignee: Sony CorporationInventors: Masatoshi Hayakawa, Koichi Aso, Yoshitaka Ochiai, Hideki Matsuda, Kazuhiko Hayashi, Wataru Ishikawa, You Iwasaki
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Patent number: 4640871Abstract: A magnetic structure having improved permeability characteristics at very high frequencies and comprising a plurality of magnetic metal layers, together with electrically insulating layers which are interposed between successive magnetic metal layers to form a laminate therewith, and at least one conductive strip electrically connecting together at least two of the magnetic metal layers, the conductive strip being of lesser width than the surface on which it is located, and serving to reduce eddy current losses.Type: GrantFiled: September 6, 1985Date of Patent: February 3, 1987Assignee: Sony CorporationInventors: Kazuhiko Hayashi, Yoshitaka Ochiai, Masatoshi Hayakawa, Hideki Matsuda, Wataru Ishikawa, You Iwasaki, Koichi Aso
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Patent number: 4639278Abstract: A method of manufacturing an amorphous alloy involves thermally treating or annealing the amorphous alloy material at a temperature lower than the crystallization temperature thereof through rotation of the alloy material relative to a magnetic field at a velocity so as to meet the following relationship:R.tau..sub.O =0.5nwhereR is the number of revolutions per minute,.tau..sub.O is an average time required to cause the amorphous alloy material to reach a thermal equilibrium state of induced magnetic anisotropy, andn is an integer of at least 1.The amorphous alloy thus prepared possesses a high permeability and a high saturated magnetic flux so that it is suitable as a soft magnetic core material, such a magnetic heads.Type: GrantFiled: December 23, 1983Date of Patent: January 27, 1987Assignee: Sony CorporationInventors: Yoshimi Makino, Yoshitaka Ochiai, Satoru Uedaira, Kazuhide Hotai, Koichi Aso, Masatoshi Hayakawa