Patents by Inventor Yoshitaka Ohtsu

Yoshitaka Ohtsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6426533
    Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: July 30, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takayuki Igarashi, Yoshitaka Ohtsu
  • Publication number: 20010023978
    Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.
    Type: Application
    Filed: May 30, 2001
    Publication date: September 27, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takayuki Igarashi, Yoshitaka Ohtsu
  • Patent number: 6281060
    Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: August 28, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takayuki Igarashi, Yoshitaka Ohtsu
  • Patent number: 6027962
    Abstract: A method of manufacturing a semiconductor device can suppress an etching damage to a bipolar transistor part and a CMOS transistor part while simplifying a manufacturing process. According to this manufacturing method, an external base leader electrode layer which will form an external base leader electrode is used as an etching protection film for forming a CMOS transistor, and a layered film including a polycrystalline silicon film which will ultimately form a gate electrode is used as an etching protection film during formation of a bipolar transistor. Thereby, a step of forming the etching protection film can be utilized also as a step of forming the external base electrode and the gate electrode. Consequently, the etching damages to the bipolar transistor part and the CMOS transistor part are suppressed while simplifying the manufacturing process.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: February 22, 2000
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takayuki Igarashi, Kakutaro Suda, Yoshitaka Ohtsu