Patents by Inventor Yoshitaka Onaya
Yoshitaka Onaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685865Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.Type: GrantFiled: May 14, 2015Date of Patent: June 20, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshio Nagasawa, Yoshitaka Onaya, Koji Saikusa, Shin Chiba
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Patent number: 9418986Abstract: A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.Type: GrantFiled: August 19, 2012Date of Patent: August 16, 2016Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Yoshitaka Onaya, Hirokazu Kato, Ryotaro Kudo, Koji Saikusa
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Publication number: 20150249387Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.Type: ApplicationFiled: May 14, 2015Publication date: September 3, 2015Inventors: Toshio NAGASAWA, Yoshitaka ONAYA, Koji SAIKUSA, Shin CHIBA
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Patent number: 9054583Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.Type: GrantFiled: December 4, 2013Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Toshio Nagasawa, Yoshitaka Onaya, Koji Saikusa, Shin Chiba
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Publication number: 20140191737Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.Type: ApplicationFiled: December 4, 2013Publication date: July 10, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshio NAGASAWA, Yoshitaka ONAYA, Koji SAIKUSA, Shin CHIBA
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Patent number: 8633550Abstract: To improve reliability of a semiconductor device A power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current flowing through the power MOSFET are formed within one semiconductor chip CPH and the semiconductor chip CPH is mounted over a chip mounting part via an electrically conductive joining material and sealed with a resin. In a main surface of the semiconductor chip CPH, a sense MOSFET region in which the sense MOSFET is formed is located more internally than a source pad PDHS4 of the sense MOSFET region RG2. Furthermore, in the main surface of the semiconductor chip, the sense MOSFET region RG2 is surrounded by a region in which the power MOSFET is formed.Type: GrantFiled: June 24, 2012Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Yoshitaka Onaya, Hirokazu Kato, Ryotaro Kudo, Koji Saikusa, Katsuhiko Funatsu
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Publication number: 20130049137Abstract: A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.Type: ApplicationFiled: August 19, 2012Publication date: February 28, 2013Inventors: Tomoaki UNO, Yoshitaka ONAYA, Hirokazu KATO, Ryotaro KUDO, Koji SAIKUSA
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Publication number: 20130001792Abstract: A power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current flowing through the power MOSFET are formed within one semiconductor chip CPH and the semiconductor chip CPH is mounted over a chip mounting part via an electrically conductive joining material and sealed with a resin. In a main surface of the semiconductor chip CPH, a sense MOSFET region in which the sense MOSFET is formed is located more internally than a source pad PDHS4 of the sense MOSFET region RG2. Furthermore, in the main surface of the semiconductor chip, the sense MOSFET region RG2 is surrounded by a region in which the power MOSFET is formed.Type: ApplicationFiled: June 24, 2012Publication date: January 3, 2013Inventors: Tomoaki UNO, Yoshitaka Onaya, Hirokazu Kato, Ryotaro Kudo, Koji Saikusa, Katsuhiko Funatsu
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Patent number: 7400278Abstract: An echo prevention circuit includes a filter that receives a first digital signal and outputs second and third digital signals; first and second DA converter that convert the second and third digital signals into first and second analog signals respectively; a circuit to subtract the second analog signal from a signal generated by combining the first analog signal and a third analog signal, a circuit to amplify the signal from the subtracting circuit; an AD converter that converts the amplified signal into a digital signal; a responsive signal acquiring unit to acquire a first response signal from the input of the first DA converter to the output of the AD converter and to acquire a second response signal from the input of the second DA converter to the output of the AD converter; and a unit to set filter coefficients based on the first and second response signals.Type: GrantFiled: March 2, 2007Date of Patent: July 15, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Takeo Inoue, Hideki Ohashi, Yoshitaka Onaya
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Patent number: 7342437Abstract: A size of a charge pump circuit is reduced as well as its cost. In a positive booster charge pump circuit in an embodiment of this invention, a positive boosted voltage 2VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level (VDD) of each of the first, third and fourth clock drivers. And in a negative charge pump circuit, a negative boosted voltage ?VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level of each of the second and fifth clock drivers.Type: GrantFiled: January 24, 2006Date of Patent: March 11, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshitaka Onaya, Tatsuya Suzuki
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Publication number: 20070205932Abstract: An echo prevention circuit comprises a filter that is inputted with a first digital signal, the filter outputting second and third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal acquired by subtracting the second analog signal from a signal generated by combining the first analog signal and the third analog signal; an amplification circuit that amplifies the signal output from the subtracting circuit and outputs the amplified signal; an AD converter that converts the signal output from the amplification circuit into a digital signal and outputs the digital signal; a response signal acquiring unit that inputs a first signal toType: ApplicationFiled: March 2, 2007Publication date: September 6, 2007Applicant: Sanyo Electric Co., Ltd.Inventors: Takeo Inoue, Hideki Ohashi, Yoshitaka Onaya
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Patent number: 7116156Abstract: An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.Type: GrantFiled: April 13, 2004Date of Patent: October 3, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Takao Myono, Yoshitaka Onaya
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Publication number: 20060164135Abstract: An abnormal reduction in a positive high power supply electric potential VH outputted by a positive booster charge pump circuit at switching of an output stage inverter in a driver circuit is prevented. An output of an inverter INV2 is applied to an input terminal of an inverter INV4 for controlling an output transistor, and an output of the inverter INV4 is applied to a gate of an N-channel type MOS transistor of the output stage inverter INV6. The inverter INV4 is made of a P-channel type MOS transistor, a first resistor and an N-channel type MOS transistor connected between a positive high power supply electric potential VH and a negative high power supply electric potential VL, making a connecting node between the first resistor and the N-channel type MOS transistor an output terminal of the inverter INV4.Type: ApplicationFiled: January 24, 2006Publication date: July 27, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Takao Myono, Yoshitaka Onaya
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Publication number: 20060164156Abstract: A size of a charge pump circuit is reduced as well as its cost. In a positive booster charge pump circuit in an embodiment of this invention, a positive boosted voltage 2 VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level (VDD) of each of the first, third and fourth clock drivers. And in a negative charge pump circuit, a negative boosted voltage ?VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level of each of the second and fifth clock drivers.Type: ApplicationFiled: January 24, 2006Publication date: July 27, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yoshitaka Onaya, Tatsuya Suzuki
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Publication number: 20040246044Abstract: An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.Type: ApplicationFiled: April 13, 2004Publication date: December 9, 2004Inventors: Takao Myono, Yoshitaka Onaya