Abstract: In a capacitor formation area A1, a capacitor C1 is formed. The capacitor is constituted by a lower-layer electrode-use polysilicon layer 105 (lower-layer electrode) formed on a LOCOS separation film 101, a nitride film 106 (dielectric film) and an upper-layer electrode-use polysilicon layer 107 (upper-layer electrode). In this case, the lower-layer electrode-use polysilicon layer 105 and the nitride film 106 are formed as the same plane pattern. In CMOS formation area A2, an NMOS transistor Q11 is formed on a P-well region 102 and a PMOS transistor Q12 is formed in an N-well region 103. Both of the gate electrodes of NMOS transistor Q11 and NMOS transistor Q21 are formed by the upper-layer electrode-use polysilicon layer 107.

Abstract: A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor substrate is rendered higher than the position of the interface between the external base electrode and the semiconductor substrate. Thus provided is a semiconductor device so improved that dispersion of the withstand voltage of a gate oxide film and dispersion of characteristics such as a threshold voltage and a drain-to-source current are reduced.

Abstract: In a capacitor formation area A1, a capacitor C1 is formed. The capacitor is constituted by a lower-layer electrode-use polysilicon layer 105 (lower-layer electrode) formed on a LOCOS separation film 101, a nitride film 106 (dielectric film) and an upper-layer electrode-use polysilicon layer 107 (upper-layer electrode). In this case, the lower-layer electrode-use polysilicon layer 105 and the nitride film 106 are formed as the same plane pattern. In CMOS formation area A2, an NMOS transistor Q11 is formed on a P-well region 102 and a PMOS transistor Q12 is formed in an N-well region 103. Both of the gate electrodes of NMOS transistor Q11 and NMOS transistor Q21 are formed by the upper-layer electrode-use polysilicon layer 107.

Abstract: A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor substrate is rendered higher than the position of the interface between the external base electrode and the semiconductor substrate. Thus provided is a semiconductor device so improved that dispersion of the withstand voltage of a gate oxide film and dispersion of characteristics such as a threshold voltage and a drain-to-source current are reduced.