Abstract: A semiconductor integrated circuit has a first output node and a second output node that complementarily outputs an oscillation signal, a capacitance circuit, an inductor, a first inverter and a second inverter connected in parallel and in opposite directions, a bias circuit that supplies a bias voltage to the capacitance circuit, and a control circuit that controls the bias circuit and supplies a reference voltage for controlling an oscillation frequency of the oscillation signal to the capacitance circuit. The capacitance circuit includes a first variable capacitance element and a second variable capacitance element connected in series, and the control circuit controls the bias voltage based on a change in an oscillation frequency of the oscillation signal when a voltage level of the reference voltage supplied to a connection node of the first variable capacitance element and the second variable capacitance element is changed in a plurality of ways.

Abstract: A semiconductor integrated circuit has a first output node and a second output node that complementarily outputs an oscillation signal, a capacitance circuit, an inductor, a first inverter and a second inverter connected in parallel and in opposite directions, a bias circuit that supplies a bias voltage to the capacitance circuit, and a control circuit that controls the bias circuit and supplies a reference voltage for controlling an oscillation frequency of the oscillation signal to the capacitance circuit. The capacitance circuit includes a first variable capacitance element and a second variable capacitance element connected in series, and the control circuit controls the bias voltage based on a change in an oscillation frequency of the oscillation signal when a voltage level of the reference voltage supplied to a connection node of the first variable capacitance element and the second variable capacitance element is changed in a plurality of ways.

Abstract: According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Abstract: According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Abstract: An electrostatic discharge (ESD) protection circuit includes first and second transistors connected in series between first and second power supply nodes. A third transistor of the ESD protection circuit turns the second transistor to OFF during normal operation. A fourth transistor of the ESD protection circuit turns the first transistor ON during ESD operation. During normal operation, a damping time constant circuit of the ESD protection circuit turns the fourth transistor OFF, and during ESD operation, turns the fourth transistor ON. A fifth transistor of the ESD protection circuit turns the second transistor ON during ESD operation. The first to fifth transistors each have a voltage resistance level that is lower than power supply voltage.