Abstract: In a gas sensor using a first FET-type sensor for a sensor unit, a gas density measurement unit measures a gas density of gas to be detected at a predetermined time on the basis of a first threshold change as a difference between a first threshold voltage applied to a first gate layer when a first source-drain current is a first threshold current while the gas to be detected is not present in the atmosphere and a second threshold voltage applied to the first gate layer when the first source-drain current is the first threshold current at the predetermined time while the gas to be detected is present in the atmosphere, and a temporal differentiation of the first threshold change.

Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.

Abstract: In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors.

Abstract: In an optical modulator 115 of an embodiment, an optical waveguide core 121 is configured from an n? type semiconductor region 134, a gate insulating film 136 on the n? type semiconductor region 134, and a p? type semiconductor region 137 on the gate insulating film 136. Further, a width W1 of the n? type semiconductor region 134 and a width W1 of the p? type semiconductor region 137 are equally formed and are layered without being shifted. Therefore, an optical modulator having stable optical characteristics can be provided.

Abstract: In a semiconductor recording device, a writing time as long as in the case where the number of bits to be subjected to ‘0’ writing is large even in the case where the number of bits to be subjected to ‘0’ writing in page writing is small. A population counter that controls the number of ‘0’ bits is provided. In addition, a writing driver is divided into a plurality of sub-writing drivers. In this configuration, as many sub-writing drivers as possible are driven as long as the number of ‘0’ writing bits is equal to or smaller than the maximum number of bits that can be simultaneously written.

Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.

Abstract: It is possible to realize a highly reliable semiconductor storage device using the semiconductor storage device which includes a plurality of memory chains including a plurality of memory cells connected in series and in which the memory cell is a storage element that performs rewrite using a cell transistor and current, the memory chain has a structure in which the storage elements are connected in parallel, a power-supply voltage and a ground voltage are supplied from an outside, and a voltage to be used for the rewrite of the storage element is lower than the ground voltage, and further, it is possible to realize the semiconductor storage device that has a large capacity, is capable of high-speed read and write, and can be manufactured with low cost.

Abstract: In an optical modulator 115 of an embodiment, an optical waveguide core 121 is configured from an n? type semiconductor region 134, a gate insulating film 136 on the n? type semiconductor region 134, and a p? type semiconductor region 137 on the gate insulating film 136. Further, a width W1 of the n? type semiconductor region 134 and a width W1 of the p? type semiconductor region 137 are equally formed and are layered without being shifted. Therefore, an optical modulator having stable optical characteristics can be provided.

Abstract: In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors.

Abstract: A semiconductor storage device includes: a semiconductor substrate; a first storage unit; a second storage unit including a plurality of the first storage units formed in a first direction parallel to the semiconductor substrate; a third storage unit including a plurality of the second storage units formed in a second direction perpendicular to the first direction and parallel to the semiconductor substrate; and a fourth storage unit including a plurality of the third storage units in a third direction perpendicular to the semiconductor substrate. A plurality of contacts coupling signal lines each configured to select an address in the second direction and the semiconductor substrate, is arranged in a region in which no interference with bit lines extending in the first direction occurs. Therefore, the semiconductor storage can perform reading and writing for large capacity at a high speed, and can be manufactured at a low cost, can be achieved.

Abstract: An object of the present invention is to reduce a pitch of selection transistors to select two directions in a semiconductor substrate surface of a three-dimensional vertical semiconductor storage device to reduce a dimension in the semiconductor substrate surface. Gates of selection transistors extending in the same direction are formed by a different process for every other gate, so that the thickness of channel semiconductor layers of the selection transistors can be reduced to almost the same thickness of the thickness of an inversion layer while the channel semiconductor layers and an electrode are contacted over a wide area. On/off control can be executed independently on the channel semiconductor layers formed at two sidewalls of the gates of the selection transistors formed at a pitch of 2F. As a result, dimensions of two directions in the semiconductor substrate surface can be set to 2F without generating double selection.

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: The purpose of the present invention is to provide a semiconductor storage device, which has small resistance in the ON state, and a small leak current in the OFF state, and which has a small-sized select transistor used therein. In this semiconductor storage device, a channel of a first select transistor that selects a memory cell array is electrically connected to each of the adjacent memory cell arrays (see FIG. 1).

Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.

Abstract: A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.