Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A magnetic head includes a coil, a main pole, a write shield, and a return path section. The return path section includes a yoke layer located on the front side in the direction of travel of a recording medium relative to the main pole, and a coupling part coupling the main pole and the yoke layer to each other. The coupling part includes a plurality of magnetic path portions that separate a magnetic flux into a plurality of fluxes and allow the fluxes to pass therethrough in parallel. The coil includes a plurality of winding portions disposed around the plurality of magnetic path portions, respectively.

Abstract: A thermally-assisted magnetic recording head includes a main pole, a waveguide, and a plasmon generator. The waveguide includes a core and a cladding. The plasmon generator is configured to excite a surface plasmon based on light propagating through the core. The plasmon generator has a front end face located in a medium facing surface, and a first inclined surface connected to the front end face and facing toward the medium facing surface. The main pole includes an interposition part interposed between the first inclined surface and the medium facing surface. The interposition part has a second inclined surface that is opposed to the first inclined surface with an insulating film interposed therebetween.

Abstract: A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section is magnetically connected to the bottom shield and is greater than the bottom shield in length in a direction perpendicular to the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other. The coil includes a first portion that passes through a space defined by the main pole and the first return path section, and a second portion that passes through a space defined by the main pole and the second return path section.

Abstract: A color processing apparatus includes a device characteristic acquisition unit configured to acquire a monitor device characteristic, a viewing condition acquisition unit configured to acquire a viewing condition of a display screen, a correction unit configured to correct the monitor device characteristic based on the viewing condition of the display screen, and a color conversion unit configured to perform color conversion based on the viewing condition of the display screen and the corrected monitor device characteristic.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: Adaptive noise reduction processing for an image including both an edge area and a smooth area produces different noise reduction effects depending on the areas. Multiple different noise reduction processing parameters are inputted, multiple pieces of corrected image data are generated for the respective noise reduction processing parameters, and correction parameters are generated corresponding to each piece of the corrected image data. Then, the multiple pieces of the corrected image data are combined based on the generated correction parameters.

Abstract: Noise in RAW image data is reduced. Parameters including pixels used as a target area and reference pixels are determined in the RAW image data, based on color filter information for the RAW image data. The RAW image data is corrected based on the parameters thus determined.

Abstract: A plasmon generator has a front end face located in a medium facing surface of a magnetic head. The plasmon generator includes a first layer formed of a first metal material, a second layer formed of a second metal material, and a third layer formed of a third metal material. Each of the second and third layers has an end portion constituting part of the front end face. The first layer does not have any portion constituting part of the front end face. The first and second metal materials are higher in electrical conductivity than the third metal material. The third metal material is higher in Vickers hardness than the first and second metal materials. The first layer has a plasmon exciting part.

Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.

Abstract: A structure and a process for a perpendicular write pole that provides increased magnetic flux at the ABS is disclosed. This is accomplished by increasing the amount of write flux that originates above the write gap, without changing the pole taper at the ABS. Three embodiment of the invention are discussed.

Abstract: A structure and a process for a perpendicular write pole that provides increased magnetic flux at the ABS is disclosed. This is accomplished by increasing the amount of write flux that originates above the write gap, without changing the pole taper at the ABS. Three embodiment of the invention are discussed.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A method of manufacturing a magnetic head includes the step of forming an accommodation part and the step of forming a return path section. The return path section lies between a main pole and a top surface of a substrate, and connects a shield and part of the main pole away from a medium facing surface to each other so that a space through which part of a coil passes is defined. The accommodation part accommodates at least part of the return path section. The step of forming the return path section forms first to third portions simultaneously. The first portion is located closer to the top surface of the substrate than is the space. The second portion is located closer to the medium facing surface than is the space. The third portion is located farther from the medium facing surface than is the space.

Abstract: A method of manufacturing a plasmon generator includes the steps of: forming an etching mask on a dielectric layer; forming an accommodation part by etching the dielectric layer using the etching mask; and forming the plasmon generator to be accommodated in the accommodation part. The step of forming the etching mask includes the steps of: forming a patterned layer on an etching mask material layer, the patterned layer having a first opening that has a sidewall; forming a structure by forming an adhesion film on the sidewall, the structure having a second opening smaller than the first opening; and etching a portion of the etching mask material layer exposed from the second opening.

Abstract: A magnetic head includes a pole layer accommodated in a groove. The pole layer has a track width defining portion and a wide portion. The pole layer includes a plurality of magnetic films stacked. At least one of the plurality of magnetic films includes a first portion included in the track width defining portion, a second portion included in the wide portion, and a third portion coupling the first and second portions to each other. In a cross section passing through the center of the pole layer taken in the track width direction, the second portion is smaller than the first portion in thickness and the top surface of the third portion is inclined with respect to a direction perpendicular to a medium facing surface.

Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.