Abstract: A serial access semiconductor memory device operable at a high speed and having a large memory capacity is disclosed. The memory device includes a plurality of memory cells divided into a plurality of addresses including an initial address and an end address, a selection circuit for sequentially selecting the memory cells from the initial address towards the end address and a reset circuit for restarting the sequential selection from the initial address, and is featured in that the memory cell or cells of the initial address are of a static type while other memory cells are of a dynamic type.