Abstract: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period.

Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.

Abstract: A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.

Abstract: A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection signal generation circuit configured to generate a region selection signal that specifies a random memory region among the memory regions, and a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal. The region selection signal generation circuit comprises a clock counter configured to count a clock signal until a reset signal is input, and a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter. The reset signal is input to the clock counter at a random timing.

Abstract: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period.

Abstract: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.

Abstract: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.

Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.

Abstract: A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.