Patents by Inventor Yoshitaka Tadaki
Yoshitaka Tadaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036224Abstract: An ultrasonic receiver encompasses a resin horn, a piezoelectric element provided at a tip of the resin horn exposed to outside, a stealth amplifier disposed at a predetermined minimum distance from the piezoelectric element, embedded in the resin horn and arranged in a behind space to which a shape of the piezoelectric element is projected, configured to change reflection characteristic of a reflection wave reflected by the stealth amplifier, and an input connection member electrically connecting between the piezoelectric element and the stealth amplifier. The predetermined minimum distance is a distance determined by design as a theoretical minimum value of an input stray-capacitance.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Inventors: Shin-ichiro UMEMURA, Yoshitaka TADAKI, Yoshiaki TAKEMOTO, Kaoru OGAYA
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Patent number: 9978723Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.Type: GrantFiled: July 7, 2017Date of Patent: May 22, 2018Assignee: OLYMPUS CORPORATIONInventors: Naohiro Takazawa, Yoshitaka Tadaki
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Publication number: 20180061779Abstract: A semiconductor device includes a first substrate, a second substrate, a first pad, a second pad, a first micro-bump, a first resin layer, and an insulating layer. The first substrate has a first semiconductor layer and a first wire layer. The second substrate has a second semiconductor layer and a second wire layer. The insulating layer contains an insulating material having hygroscopic properties lower than hygroscopic properties of the first resin layer. The insulating layer penetrates the second substrate and the first resin layer. The insulating layer surrounds the first micro-bump in a first cross section which passes through the first micro-bump, the first resin layer, and the insulating layer and is parallel to the first surface.Type: ApplicationFiled: November 2, 2017Publication date: March 1, 2018Applicant: OLYMPUS CORPORATIONInventors: Naohiro Takazawa, Yoshitaka Tadaki
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Publication number: 20170309599Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.Type: ApplicationFiled: July 7, 2017Publication date: October 26, 2017Applicant: OLYMPUS CORPORATIONInventors: Naohiro Takazawa, Yoshitaka Tadaki
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Patent number: 9478520Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.Type: GrantFiled: August 27, 2014Date of Patent: October 25, 2016Assignee: OLYMPUS CORPORATIONInventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
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Publication number: 20150357300Abstract: A semiconductor substrate includes a semiconductor substrate body in which a wiring is formed and a bonding electrode provided to protrude from a first surface of the semiconductor substrate body. The bonding electrode comprises a composite including a first metal portion which is provided to protrude from the first surface of the semiconductor substrate body and of which a base end portion in a protrusion direction is electrically connected to the wiring, and a second metal portion which is formed of a second metal which has lower hardness than first metal of which the first metal portion is formed and which is provided to be bonded to the first metal portion in a range equal to or less than a protrusion height of the first metal portion, the first metal portion is formed on the second metal portion by sputtering or evaporation the first metal.Type: ApplicationFiled: August 11, 2015Publication date: December 10, 2015Applicant: OLYMPUS CORPORATIONInventors: Haruhisa Saito, Yoshitaka Tadaki, Chihiro Migita
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Publication number: 20150311146Abstract: A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.Type: ApplicationFiled: July 9, 2015Publication date: October 29, 2015Applicant: OLYMPUS CORPORATIONInventors: Chihiro Migita, Hiroshi Kikuchi, Yoshiaki Takemoto, Yoshitaka Tadaki
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Patent number: 9111923Abstract: A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.Type: GrantFiled: March 15, 2013Date of Patent: August 18, 2015Assignee: OLYMPUS CORPORATIONInventors: Chihiro Migita, Hiroshi Kikuchi, Yoshiaki Takemoto, Yoshitaka Tadaki
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Patent number: 8963346Abstract: A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body.Type: GrantFiled: March 18, 2013Date of Patent: February 24, 2015Assignee: Olympus CorporationInventors: Haruhisa Saito, Yoshitaka Tadaki
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Publication number: 20140367853Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Applicant: OLYMPUS CORPORATIONInventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
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Patent number: 8847296Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.Type: GrantFiled: January 16, 2013Date of Patent: September 30, 2014Assignee: Olympus CorporationInventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
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Patent number: 8754489Abstract: An ultrasonic transducer includes a first electrode, a first insulation film covering the first electrode, a hollow part overlapping the first electrode on the first insulation film, a second insulation film covering the hollow part, a second electrode overlapping the hollow part on the second insulation film, and an interconnection joined to the second electrode. An edge of the first electrode is formed so as to moderate a step of the first electrode.Type: GrantFiled: September 6, 2012Date of Patent: June 17, 2014Assignee: Hitachi, Ltd.Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki
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Publication number: 20130256879Abstract: A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.Type: ApplicationFiled: March 15, 2013Publication date: October 3, 2013Applicant: OLYMPUS CORPORATIONInventors: Chihiro Migita, Hiroshi Kikuchi, Yoshiaki Takemoto, Yoshitaka Tadaki
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Publication number: 20130256839Abstract: A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body.Type: ApplicationFiled: March 18, 2013Publication date: October 3, 2013Applicant: OLYMPUS CORPORATIONInventors: Haruhisa Saito, Yoshitaka Tadaki
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Publication number: 20120326556Abstract: An ultrasonic transducer includes a first electrode, a first insulation film covering the first electrode, a hollow part overlapping the first electrode on the first insulation film, a second insulation film covering the hollow part, a second electrode overlapping the hollow part on the second insulation film, and an interconnection joined to the second electrode. An edge of the first electrode is formed so as to moderate a step of the first electrode.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Inventors: Shuntaro MACHIDA, Hiroyuki ENOMOTO, Yoshitaka TADAKI
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Patent number: 8294225Abstract: This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.Type: GrantFiled: March 19, 2009Date of Patent: October 23, 2012Assignee: Hitachi, Ltd.Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki
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Patent number: 8198782Abstract: An ultrasonic transducer includes a first electrode, a second electrode, an insulating film disposed between the first and second electrodes, and a cavity disposed between the first and second electrodes. The insulating film includes a projection extending in the cavity, and a portion of the cavity is disposed between the projection and the first electrode. A portion of one of the first electrode and the second electrode has an opening corresponding to a position of the projection of the insulating film when viewed in plan view.Type: GrantFiled: March 1, 2010Date of Patent: June 12, 2012Assignee: Hitachi, Ltd.Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
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Publication number: 20100148594Abstract: An ultrasonic transducer includes a first electrode, a second electrode, an insulating film disposed between the first and second electrodes, and a cavity disposed between the first and second electrodes. The insulating film includes a projection extending in the cavity, and a portion of the cavity is disposed between the projection and the first electrode. A portion of one of the first electrode and the second electrode has an opening corresponding to a position of the projection of the insulating film when viewed in plan view.Type: ApplicationFiled: March 1, 2010Publication date: June 17, 2010Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
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Patent number: 7675221Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.Type: GrantFiled: July 20, 2006Date of Patent: March 9, 2010Assignee: Hitachi, Ltd.Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
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Publication number: 20090189480Abstract: This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.Type: ApplicationFiled: March 19, 2009Publication date: July 30, 2009Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki