Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.

Abstract: Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.

Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.

Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.

Abstract: A semiconductor device (1) includes a first processing unit (10-1), a second processing unit (10-2), a writing unit (12), a storage unit (14), and a processing control unit (20). The writing unit (12) writes first information related to processing of each of the first processing unit (10-1) and the second processing unit (10-2) into the storage unit (14). The processing control unit (20) controls the operations of the first processing unit (10-1) and the second processing unit (10-2). The processing control unit (20) performs control to stop the first processing unit (10-1) when an error occurs in the first processing unit (10-1). When it is determined that the second processing unit (10-2) where an error has not occurred is able to maintain execution of the first processing by using first information stored in the storage unit (14), the second processing unit (10-2) maintains execution of the first processing.

Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.

Abstract: Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.

Abstract: A semiconductor device includes a first circuit and a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit. A pattern-generator control circuit controls each of the plurality of pattern generators such that the pattern generator starts to operate when a control signal is at a first level and the pattern generator stops operating when the control signal is not at the first level. A pattern compressor compresses a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators. A pattern-compressor control circuit controls the pattern compressor.

Abstract: A semiconductor device (1) includes a first processing unit (10-1), a second processing unit (10-2), a writing unit (12), a storage unit (14), and a processing control unit (20). The writing unit (12) writes first information related to processing of each of the first processing unit (10-1) and the second processing unit (10-2) into the storage unit (14). The processing control unit (20) controls the operations of the first processing unit (10-1) and the second processing unit (10-2). The processing control unit (20) performs control to stop the first processing unit (10-1) when an error occurs in the first processing unit (10-1). When it is determined that the second processing unit (10-2) where an error has not occurred is able to maintain execution of the first processing by using first information stored in the storage unit (14), the second processing unit (10-2) maintains execution of the first processing.

Abstract: A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.

Abstract: A semiconductor device includes a plurality of processing units, a shared resource shared by the plurality of processing units, and a guard unit. The guard unit restricts and thereby controls access to the shared resource by a processing unit, and changes, when a processing unit has failed, control of access so that another processing unit that takes over a process of the failed processing unit is permitted to access at least a part of an access destination which the failed processing unit has been permitted to access.

Abstract: A life determining device capable of performing life determination while suppressing a processing load is provided. A life determining device 1 includes a measured value acquiring unit 2 that acquires a measured value for a stressor at predetermined time intervals, an acceleration factor acquiring unit 3 that acquires a first acceleration factor, which is the ratio of a second life to a first life, at predetermined time intervals, and a life determining unit 5 that determines life expiration of a device whose life is to be determined by comparing a value obtained by multiplying an accumulated value of the first acceleration factor by a predetermined time with a second life. The acceleration factor acquiring unit 3 uses a look-up table 4 that stores a second acceleration factor for each predetermined value when it acquires the first acceleration factor.

Abstract: An optical transmission system includes: a transmission node to transmit wavelength-multiplexed light of a plural wavelengths arranged in a predetermined transmission band; and a reception node to receive the wavelength-multiplexed light, and to include a monitor to monitor a detection sensitivity indicating a sampling phase shift with respect to a phase of light corresponding to one among the received plural wavelengths, and a transmitter to transmit information indicating that the monitored detection sensitivity for light corresponding to a wavelength adjacent to an outer edge of the transmission band, among the plural wavelengths, has been reduced below a threshold value, to the transmission node, wherein the transmission node includes a receiver to receive information indicating a reduction in the detection sensitivity, and a controller to stop wavelength control of shifting the wavelength adjacent to the outer edge in a direction approaching the outer edge in response to reception of the information.

Abstract: In a memory with ECC, a failure detection rate of an address circuit of the memory is improved without using address information to generate redundant bits and without rewriting the memory. The memory stores data of addresses different from each other and redundant bits added to the data in a plurality of memory cells sharing the same selection signal wiring (for example, a word line or a column line) and outputs read-out data corresponding to a specified address. An ECC decoder performs error detection on the read-out data. When an error is detected by the ECC decoder, a failure diagnosis of the memory is performed by accessing one or a plurality of addresses which are selected by the same selection signal wiring as selection signal wiring that selects read-out data where the error is detected and which are different from the address of the read-out data and evaluating a result of the error detection for the read-out data.

Abstract: An optical transmission system includes: a transmission node to transmit wavelength-multiplexed light of a plural wavelengths arranged in a predetermined transmission band; and a reception node to receive the wavelength-multiplexed light, and to include a monitor to monitor a detection sensitivity indicating a sampling phase shift with respect to a phase of light corresponding to one among the received plural wavelengths, and a transmitter to transmit information indicating that the monitored detection sensitivity for light corresponding to a wavelength adjacent to an outer edge of the transmission band, among the plural wavelengths, has been reduced below a threshold value, to the transmission node, wherein the transmission node includes a receiver to receive information indicating a reduction in the detection sensitivity, and a controller to stop wavelength control of shifting the wavelength adjacent to the outer edge in a direction approaching the outer edge in response to reception of the information.

Abstract: A transmission system includes: a first transmission device configured to transmit an input signal to a second transmission device via a transmission section, the first transmission device preforms operations of: saving overhead information included in a first frame of the input signal from a region in use to an unused region of the first frame, the overhead information corresponding to an object of termination in the transmission section; and transmitting, to the transmission section, a first signal including a second frame in which the overhead information is saved.

Abstract: A transmission apparatus includes a generation unit configured to generate a first data unit including a second data unit, and an addition unit configured to add fault data indicating a fault state of the second data unit to a data portion different from a data portion in which the second data unit is positioned within the first data unit.

Abstract: An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example.

Abstract: An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example.

Abstract: In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN (“0”-“31”)) are assigned are cyclically generated respectively for paths P0-P2 in a cycle TC (=64 ms). After output timing delays TD0-TD2 of the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P0-P2 based on the number of the paths “3”, the output timing delays TD1 and TD2 are restored by preliminarily obtained transmission delays for the paths P1 and P2 to the path P0. When the frames FR are transmitted through each of the paths P0-P2, statuses (path statuses MST) where a reception fault has occurred in each of the paths P0-P2 are collected to be stored in the frame whose frame No. FN=“0”.