Abstract: A rounding operation circuit for arithmetic logic unit of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic unit for adding the output signal of this decoder circuit and the first input signal; and a rounding circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation

Abstract: A signal processing circuit includes an instruction memory for storing arithmetic instructions, a instruction decoder for decoding the instructions read from the instruction memory, an arithmetic circuit for carrying out arithmetic process in accordance with the instructions decoded by the instruction decoder, data memory for storing data to be processed by the arithmetic circuit, and a multi-port type register for storing data read from the data memory and the results of the arithmetic results. In the signal processing circuit, arithmetic processes in the arithmetic circuit are carried out in parallel by transferring data between the multi-port type register and the arithmetic circuit in accordance with one instruction.