Abstract: A storage device for storing a column store database, the storage device comprising: a column read unit which reads page data to be searched that have been read from the column store database, acquires a leading row number included in the page data, and reads each column of data in the page data, sequentially from the leading row number to the last row in the column of data; a data search unit which compares each row in each read column of data with first search criteria, from the first row to the last row, and outputs a comparison result; and a search result aggregation unit which, when a comparison result for a range of columns specified by a search request has been output, compares each row in the comparison result with second search criteria, and determines one or more rows in the comparison result that satisfy the second search criteria.

Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.

Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.

Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.

Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.

Abstract: A storage device for storing a column store database, the storage device comprising: a column read unit which reads page data to be searched that have been read from the column store database, acquires a leading row number included in the page data, and reads each column of data in the page data, sequentially from the leading row number to the last row in the column of data; a data search unit which compares each row in each read column of data with first search criteria, from the first row to the last row, and outputs a comparison result; and a search result aggregation unit which, when a comparison result for a range of columns specified by a search request has been output, compares each row in the comparison result with second search criteria, and determines one or more rows in the comparison result that satisfy the second search criteria.

Abstract: A computer comprising a processor and a memory and providing a database management unit for managing a database, said computer having a device that is connected to the processor via an interface and that comprises: at least one nonvolatile semiconductor storage device which has a plurality of nonvolatile semiconductor memories and which stores a database; at least one database calculation module which reads the database from the nonvolatile semiconductor storage device and performs calculations in the database; and a switch which connects the interface to the nonvolatile semiconductor storage device and the database calculation module.

Abstract: A database search system receives a command and searches for data, which meets a search condition specified on the basis of the received command, in a whole database which is a database as an entity. The database search system generates a virtual database which is a list of address pointers to the found data and stores the generated virtual database.

Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.

Abstract: A storage apparatus to be coupled to a network, the storage apparatus comprising: a controller; and a storage medium to be coupled to the controller, the storage medium comprising one or more flash modules each comprising a database operation module, the controller being configured to receive a database operation command, and to cause the one or more flash modules to execute the received database operation command.

Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.

Abstract: A transceiver system which can communicate a plurality of linked partners, and the increase in power consumption by the transceiver system can be minimized. The transceiver system includes a transceiver, and a communication controller. The transceiver is capable of performing transmitted and received data communication with terminal devices. The communication controller is capable of controlling the memory transfer of transmitted and received data. The transceiver system can be set to an operation mode selected from among intermittent- and uninterrupted-operation modes. In the intermittent-operation mode, the transceiver and the communication controller work alternately, whereas in the uninterrupted-operation mode, the transceiver and the communication controller works in parallel. The operation mode of the transceiver system is set according to unique identification data of terminal devices.

Abstract: A transceiver system which can communicate a plurality of linked partners, and the increase in power consumption by the transceiver system can be minimized. The transceiver system includes a transceiver, and a communication controller. The transceiver is capable of performing transmitted and received data communication with terminal devices. The communication controller is capable of controlling the memory transfer of transmitted and received data. The transceiver system can be set to an operation mode selected from among intermittent- and uninterrupted-operation modes. In the intermittent-operation mode, the transceiver and the communication controller work alternately, whereas in the uninterrupted-operation mode, the transceiver and the communication controller works in parallel. The operation mode of the transceiver system is set according to unique identification data of terminal devices.

Abstract: The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit.

Abstract: A transceiver system which can communicate a plurality of linked partners, and the increase in power consumption by the transceiver system can be minimized. The transceiver system includes a transceiver, and a communication controller. The transceiver is capable of performing transmitted and received data communication with terminal devices. The communication controller is capable of controlling the memory transfer of transmitted and received data. The transceiver system can be set to an operation mode selected from among intermittent- and uninterrupted-operation modes. In the intermittent-operation mode, the transceiver and the communication controller work alternately, whereas in the uninterrupted-operation mode, the transceiver and the communication controller works in parallel. The operation mode of the transceiver system is set according to unique identification data of terminal devices.

Abstract: The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit.

Abstract: The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit.

Abstract: The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit.