Patents by Inventor Yoshitake Hayashi
Yoshitake Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8745859Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.Type: GrantFiled: May 16, 2012Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Shozo Ochi, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
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Publication number: 20120293965Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: Panasonic CorporationInventors: Shozo OCHI, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
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Patent number: 7737367Abstract: Holes having the same diameter as via holes are formed in predetermined positions in advance when forming wiring patterns on releasable carriers. The carriers with the wiring patterns are bonded on an insulating material, and a laser beam is irradiated from the side of the carrier using the holes in the wiring pattern as a laser mask to form via holes in the insulating material. The via holes and the holes in the carrier are then filled with a conductive paste. With the holes in the carrier that are matched in position with the via holes, lands in the conductor layers are precisely positioned relative to the via holes. A multilayer circuit board thus produced has lower electrical connection resistance and excellent mountability with improved performances. Also a manufacturing method thereof is achieved.Type: GrantFiled: January 25, 2006Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventors: Masayoshi Koyama, Yoshitake Hayashi, Kazuo Otani
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Patent number: 7488895Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.Type: GrantFiled: September 27, 2004Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Yasushi Taniguchi, Seiichi Nakatani
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Publication number: 20070119617Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.Type: ApplicationFiled: September 27, 2004Publication date: May 31, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Seiichi Nakatani
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Publication number: 20060191715Abstract: Holes having the same diameter as via holes are formed in predetermined positions in advance when forming wiring patterns on releasable carriers. The carriers with the wiring patterns are bonded on an insulating material, and a laser beam is irradiated from the side of the carrier using the holes in the wiring pattern as a laser mask to form via holes in the insulating material. The via holes and the holes in the carrier are then filled with a conductive paste. With the holes in the carrier that are matched in position with the via holes, lands in the conductor layers are precisely positioned relative to the via holes. A multilayer circuit board thus produced has lower electrical connection resistance and excellent mountability with improved performances. Also a manufacturing method thereof is achieved.Type: ApplicationFiled: January 25, 2006Publication date: August 31, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masayoshi Koyama, Yoshitake Hayashi, Kazuo Otani
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Publication number: 20060087020Abstract: In a semiconductor device, circuit boards are connected electrically to each other by via-conductors that penetrate sheet members, semiconductor elements arranged between substrates are contained in element-containing portions formed on the sheet members, and a low-elastic material whose elastic modulus is lower than the elastic modulus of the thermosetting resin composition of the sheet members is filled in the space between the semiconductor elements contained in the element-containing portions and the substrates opposing surfaces opposite to the mounting surfaces of the semiconductor elements. Thereby, a semiconductor device resistant to warping and deformation and having a high mounting reliability is provided.Type: ApplicationFiled: October 20, 2005Publication date: April 27, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Koichi Hirano, Seiichi Nakatani, Tsukasa Shiraishi, Yoshitake Hayashi
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Patent number: 6898850Abstract: A method of manufacturing a circuit board by forming a circuit pattern in a short process and capable of performing pattern transfer with stability. The manufacturing method includes a step of superposing on a carrier a resist layer in which a circuit pattern is formed and which is formed of a conductor or an insulator, a step of filling the circuit pattern with an electroconductive material, a step of removing the resist layer from the carrier, and a step of transferring the electroconductive material filled in the circuit pattern into an electrical insulating material.Type: GrantFiled: August 4, 2003Date of Patent: May 31, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideo Kanzawa, Satoru Yuuhaku, Yoshitake Hayashi
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Publication number: 20040078969Abstract: A method of manufacturing a circuit board by forming a circuit pattern in a short process and capable of performing pattern transfer with stability. The manufacturing method includes a step of superposing on a carrier a resist layer in which a circuit pattern is formed and which is formed of a conductor or an insulator, a step of filling the circuit pattern with an electroconductive material, a step of removing the resist layer from the carrier, and a step of transferring the electroconductive material filled in the circuit pattern into an electrical insulating material.Type: ApplicationFiled: August 4, 2003Publication date: April 29, 2004Inventors: Hideo Kanzawa, Satoru Yuuhaku, Yoshitake Hayashi
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Patent number: 6613180Abstract: A method for fabricating a semiconductor-mounting body having at least one semiconductor device mounted on a substrate and a sealing resin set in the gap between the substrate and the semiconductor device, has a first step of setting a flexibly deformable sheet on a face of the semiconductor device not facing the substrate; and a second step of generating an air-pressure difference between the side where the semiconductor device is not present and the side where the semiconductor device is present on the basis of the sheet so that the air pressure at the side where the semiconductor device is not present becomes higher than the side where the semiconductor device is present and pressurizing the semiconductor device by the sheet after the first step.Type: GrantFiled: April 1, 2002Date of Patent: September 2, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshitaka Sunagawa, Yoshitake Hayashi, Masayoshi Koyama, Yoshihiro Tomura, Toshiyuki Kojima, Osamu Shibata, Ryuichi Saito
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Publication number: 20030027371Abstract: A method for fabricating a semiconductor-mounting body having at least one semiconductor device mounted on a substrate and a sealing resin set in the gap between the substrate and the semiconductor device, hasType: ApplicationFiled: April 1, 2002Publication date: February 6, 2003Inventors: Yoshitaka Sunagawa, Yoshitake Hayashi, Masayoshi Koyama, Yoshihiro Tomura, Toshiyuki Kojima, Osamu Shibata, Ryuichi Saito
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Patent number: 4791815Abstract: A gyro which realizes a small error response to a disturbance inertia such as vibration, impact, etc. and an adjusting system thereof has a pair of mass elements which are cyclically driven symmetrically. A pair of sensors independently detect forces produced in response to an input angular rate and generate a pair of detection outputs. An adjustable adder synthesizes components proportional to the disturbance inertia contained in the detection outputs with an optimum addition ratio so that they are mutually completely cancelled and generates a synthesized output. A signal processing circuit processes the synthesized output to generate an output proportional to the input angular rate. The adjusting system applies to the gyro in an operating condition a disturbance vibration in the vicinity of the drive frequency of the gyro. By adjusting the addition ratio of the adjustable adder in a manner so as to make the response at this time a minimum, the best characteristic can be obtained.Type: GrantFiled: April 3, 1987Date of Patent: December 20, 1988Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Yamaguchi, Suzushi Kimura, Yoshitake Hayashi
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Patent number: 4633032Abstract: A package configuration of a solar cell has a glass substrate having a solar cell element formed on the surface opposite to the light-receiving surface thereof, a backplate disposed across an empty space from the surface of the glass substrate opposite to the light receiving surface thereof, a frame connecting the glass substrate and the backplate to each other along the peripheries thereof, a sealing resin layer sealed inside the peripheries of the backplate and the frame so as to isolate the empty space from the atmosphere, a layer of desiccant disposed inside the backplate so as to adsorb moisture penetrating into the empty space, and conductor wires for externally collecting electric energy generated by the solar cell element.Type: GrantFiled: February 13, 1985Date of Patent: December 30, 1986Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hikofumi Oido, Yoshitake Hayashi, Minoru Yamamoto