Patents by Inventor Yoshitake Kato
Yoshitake Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10658469Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.Type: GrantFiled: May 1, 2014Date of Patent: May 19, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiro Iizuka, Shin Koyama, Yoshitake Kato
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Patent number: 10374053Abstract: The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb.Type: GrantFiled: March 30, 2015Date of Patent: August 6, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshitake Kato
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Publication number: 20170317183Abstract: The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb.Type: ApplicationFiled: March 30, 2015Publication date: November 2, 2017Inventor: Yoshitake KATO
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Publication number: 20170073570Abstract: A cellulose fiber nano-dispersion pressing-in device for pressing a liquid, in which a cellulose fiber of a conifer-derived pulp is nano-dispersed, into a stratum, includes a grinding means for grinding the conifer-derived pulp in water, a dilution means for diluting a cellulose fiber-containing liquid obtained in the grinding means and a pressing-in means for pressing a nano-dispersion of the cellulose fiber obtained in the dilution means into a well. Therefore, it is applicable to water-stopping operation in a civil engineering process or to a process of industrial production of hydrocarbons such as crude oil, gas and the like for improving the recovery rate thereof.Type: ApplicationFiled: November 25, 2014Publication date: March 16, 2017Applicant: DAI-ICHI KOGYO SEIYAKU CO., LTD.Inventors: Yosuke GOI, Mineo SABI, Kazuhito JINNO, Koji NODA, Yoshitake KATO, Norihiko TOGASHI, Yosuke KUNISHI
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Publication number: 20170047409Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.Type: ApplicationFiled: May 1, 2014Publication date: February 16, 2017Inventors: Toshihiro IIZUKA, Shin KOYAMA, Yoshitake KATO
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Patent number: 9379178Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.Type: GrantFiled: August 26, 2015Date of Patent: June 28, 2016Assignee: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Publication number: 20160071850Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.Type: ApplicationFiled: November 3, 2015Publication date: March 10, 2016Inventors: Misato SAKAMOTO, Yoshitake KATO, Youichi YAMAMOTO, Hitoshi KASAI, Satoshi ITOU
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Publication number: 20150372074Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.Type: ApplicationFiled: August 26, 2015Publication date: December 24, 2015Inventors: Youichi YAMAMOTO, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Patent number: 9209189Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.Type: GrantFiled: March 18, 2015Date of Patent: December 8, 2015Assignee: Renesas Electronics CorporationInventors: Misato Sakamoto, Yoshitake Kato, Youichi Yamamoto, Hitoshi Kasai, Satoshi Itou
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Publication number: 20150270271Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.Type: ApplicationFiled: March 18, 2015Publication date: September 24, 2015Inventors: Misato SAKAMOTO, Yoshitake KATO, Youichi YAMAMOTO, Hitoshi KASAI, Satoshi ITOU
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Patent number: 9142609Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.Type: GrantFiled: January 12, 2011Date of Patent: September 22, 2015Assignee: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Patent number: 8940601Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.Type: GrantFiled: July 6, 2012Date of Patent: January 27, 2015Assignee: Renesas Electronics CorporationInventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
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Patent number: 8685866Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.Type: GrantFiled: June 24, 2010Date of Patent: April 1, 2014Assignees: Hitachi Kokusai Electric, Inc., Renesas Electronics Corp.Inventors: Sadayoshi Horii, Atsushi Sano, Masahito Kitamura, Yoshitake Kato
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Publication number: 20130011994Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.Type: ApplicationFiled: July 6, 2012Publication date: January 10, 2013Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
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Publication number: 20110169132Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.Type: ApplicationFiled: January 12, 2011Publication date: July 14, 2011Applicant: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Publication number: 20110008955Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.Type: ApplicationFiled: June 24, 2010Publication date: January 13, 2011Applicants: HITACHI-KOKUSAI ELECTRIC INC., NEC ELECTRONICS CORP.Inventors: Sadayoshi HORII, Atsushi SANO, Masahito KITAMURA, Yoshitake KATO
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Patent number: 7672575Abstract: In an evaporator for evaporating mists of liquid raw material to thereby generate start gas for layer-formation, an evaporator body has an evaporator chamber defined therein, and a mist supply throat for introducing the mists into the evaporating chamber. The evaporator chamber is defined by a principal evaporating face which opposes to the mist supply throat. The evaporator body also has a start-gas supply passage which is formed therein between the mist supply throat and the principal evaporating face such that the start gas flows out of the evaporating chamber through the start-gas supply passage. A ridge member is provided on an inner side wall surface of the evaporating chamber between the start-gas is supply passage and the principal evaporating face so that a tip edge of the ridge member is directed to the principal evaporating face.Type: GrantFiled: November 6, 2006Date of Patent: March 2, 2010Assignee: NEC Electronics CorporationInventor: Yoshitake Kato
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Patent number: 7608502Abstract: In the process for manufacturing a semiconductor device of the present invention, a capacitor dielectric film is deposited via an atomic layer deposition employing an organic source material containing one or more metallic element(s) selected from the group consisting of Zr, Hf, La and Y as a deposition gas. The process for manufacturing a capacitor of the present invention includes obtaining a boundary temperature T (degree C.), at which an increase in a deposition rate for depositing the capacitor dielectric film as increasing the temperature is detected, on the basis of a correlation data of a deposition temperature in the atomic layer deposition employing the deposition gas with a deposition rate for depositing the capacitor dielectric film at the deposition temperature (S100 and S102); and depositing the capacitor dielectric film via the atomic layer deposition employing the deposition gas at a temperature within a range of from (T?20) (degree C.) to (T+20) (degree C.) (S104 to S112).Type: GrantFiled: August 19, 2005Date of Patent: October 27, 2009Assignee: NEC Electronics CorporationInventors: Tomohisa Iino, Naomi Fukumaki, Yoshitake Kato, Tomoe Yamamoto
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Publication number: 20090217873Abstract: An atomic layer deposition apparatus includes: a metal source gas supply tube, disposed in a side of a wafer to extend over the entire surface of the wafer, and capable of being supplied with a source gas from a first end to a second end; and an active gas supply tube, disposed in a side of a wafer to extend over the entire surface of the wafer, and capable of being supplied with a source gas from a first end to a second end, wherein the active gas supply tube is provided with a plurality of gas blow openings for blowing the active gas that is active over the wafer, and wherein the gas blow openings are disposed with gradually reduced inter-opening distances as being further from the first end to the second end of the active gas supply tube.Type: ApplicationFiled: February 13, 2009Publication date: September 3, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomohisa Iino, Naomi Fukumaki, Yoshitake Kato
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Publication number: 20090057739Abstract: The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface layer (4) functions to suppress the diffusion of Ge atoms into the La2O3 layer (6) and thereby prevents the formation of Ge oxide in the La2O3 layer (6); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.Type: ApplicationFiled: August 28, 2008Publication date: March 5, 2009Applicant: Tokyo Institute of TechnologyInventors: Hiroshi Iwai, Takeo Hattori, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, Jaeyeol Song, Masaki Yoshimaru, Yasuyoshi Mishima, Tomonori Aoyama, Hiroshi Oji, Yoshitake Kato