Patents by Inventor Yoshiteru Ochi

Yoshiteru Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190281690
    Abstract: A cooling system includes a heat exchanger provided on a heat generating component, the heat exchanger having a size larger than the heat generating component, a leaf spring to extend from a first side of an upper surface of the heat exchanger to a second side opposite to the first side, and be fixed to the upper surface of the heat exchanger, a first screw to be arranged around the heat exchanger, and to fix the leaf spring to a printed circuit board, and a convex portion to be raised to be higher than a first portion of the first side and a second portion of the second side, and to be formed at a central portion between first and second portions within a region of the upper surface of the heat exchanger that overlaps with the leaf spring.
    Type: Application
    Filed: February 1, 2019
    Publication date: September 12, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiteru OCHI, Hidehisa Sakai
  • Publication number: 20180135920
    Abstract: An electronic device includes a heat exchanger that includes a flat tube through which fluid flows. The flat tube includes a tube main body section, a connecting wall portion, and a flange portion. The tube main body section has a join portion at which an outer face at one end side of the tube main body section and an inner face at another end side of the tube main body section are joined together in an overlapping state to form a flat tube shape. The connecting wall portion extends from the one end of the tube main body section toward the inside of the tube main body section. The flange portion extends along the inner face of the tube main body section from a leading end part of the connecting wall portion toward an opposite side from the join portion, and is joined to the inner face.
    Type: Application
    Filed: October 16, 2017
    Publication date: May 17, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiteru OCHI, Hidehisa Sakai, Tsuyoshi So, Hideo Kubo
  • Publication number: 20140239488
    Abstract: An electronic component unit includes a semiconductor package mounted on a front surface of a substrate, a heat sink including a pushing plate installed on the semiconductor package, a reinforcing plate disposed on a back surface of the substrate, and a plurality of fasteners that connect corner portions of the pushing plate and the reinforcing plate to each other, wherein the semiconductor package is pressed and fixed on the substrate by fastening the plurality of fasteners, and the reinforcing plate includes a base plate portion including a connection portion to which each of the plurality of fasteners is connected, and a pressing plate portion which is disposed at a planar central side of the base plate portion, and separably laminated on the base plate portion to press the back surface of the substrate.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 28, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Yoko KOBAYASHI, Tsuyoshi SO, Nobutaka ITOH, Yoshiteru OCHI, Katsuhiko NAKATA
  • Patent number: 8744810
    Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Limited
    Inventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
  • Patent number: 8378220
    Abstract: An electronic device includes, a circuit board including a through hole, a member including a screw hole, a screw including a screw body having an outer diameter smaller than an inner diameter of the through hole and a screw head having an outer diameter larger than the inner diameter of the through hole, wherein the screw body penetrates through the through hole to engage with the screw hole and the screw head is disposed on an opposite side of the circuit board to the member, and a first washer provided between the screw head and the circuit board, the first washer including a first washer body and a plurality of first washer legs extending from the first washer body toward the circuit board, the first washer legs being in contact with the circuit board and having a characteristic of reducing stress on the circuit board upon being heated.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Fujitsu Limited
    Inventors: Yoshiteru Ochi, Nobutaka Itoh, Makoto Sakairi
  • Patent number: 8083528
    Abstract: A connector includes a contact pin in which a free end projecting from a supporting member comes into contact with an electrode of a first object and a second object, and a bending part is provided onto a base end such that the connector has an inclination against the first object and the second object. The rigidity of the bending parts is selectively set to be high by selectively increasing a thickness of the bending part.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Limited
    Inventors: Makoto Sakairi, Nobutaka Itoh, Yoshiteru Ochi, Yoko Kobayashi
  • Publication number: 20110208485
    Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 25, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Nobutaka ITOH, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
  • Publication number: 20110085305
    Abstract: An electronic device includes, a circuit board including a through hole, a member including a screw hole, a screw including a screw body having an outer diameter smaller than an inner diameter of the through hole and a screw head having an outer diameter larger than the inner diameter of the through hole, wherein the screw body penetrates through the through hole to engage with the screw hole and the screw head is disposed on an opposite side of the circuit board to the member, and a first washer provided between the screw head and the circuit board, the first washer including a first washer body and a plurality of first washer legs extending from the first washer body toward the circuit board, the first washer legs being in contact with the circuit board and having a characteristic of reducing stress on the circuit board upon being heated.
    Type: Application
    Filed: September 22, 2010
    Publication date: April 14, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiteru OCHI, Nobutaka Itoh, Makoto Sakairi
  • Patent number: 7725866
    Abstract: When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume, height, and connection area of the solder connection part. By means of dividing the solder connection model into multiple meshes, the first mesh data for use in electronic package analysis is created.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: May 25, 2010
    Assignee: Fujitsu Limited
    Inventors: Yoko Kobayashi, Hidehisa Sakai, Yoshiteru Ochi
  • Publication number: 20090325401
    Abstract: A connector includes a contact pin in which a free end projecting from a supporting member comes into contact with an electrode of a first object and a second object, and a bending part is provided onto a base end such that the connector has an inclination against the first object and the second object. The rigidity of the bending parts is selectively set to be high by selectively increasing a thickness of the bending part.
    Type: Application
    Filed: September 3, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Makoto Sakairi, Nobutaka Itoh, Yoshiteru Ochi, Yoko Kobayashi
  • Publication number: 20090324095
    Abstract: An analysis-model-producing apparatus for producing an analysis model from a shape model, comprising means for specifying a deletion method for deleting, from geometric shape data constituting the shape model, geometric shape data that is unnecessary to production of an analysis model, and means for deleting unnecessary data, using the specified deletion method.
    Type: Application
    Filed: September 9, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Makoto Sakairi, Nobutaka Itoh, Yoshiteru Ochi, Yoko Kobayashi
  • Patent number: 7476814
    Abstract: A multilayer interconnection board includes a plurality of stacked insulation layers, wiring layers in the insulation layers, and via forming parts for interlayer connection, the via forming parts piercing the insulation layers. In the multilayer interconnection board, 0<L2?(L1/3) is set, where L1 denotes the distance between center positions of a pair of neighboring via forming parts formed in the same insulation layer and L2 denotes the shortest separation distance between the pair of the via forming parts.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: January 13, 2009
    Assignee: Fujitsu Limited
    Inventors: Yoshiteru Ochi, Nobutaka Itoh
  • Publication number: 20080127011
    Abstract: When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume, height, and connection area of the solder connection part. By means of dividing the solder connection model into multiple meshes, the first mesh data for use in electronic package analysis is created.
    Type: Application
    Filed: September 14, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yoko KOBAYASHI, Hidehisa Sakai, Yoshiteru Ochi
  • Publication number: 20080017412
    Abstract: A multilayer interconnection board includes a plurality of stacked insulation layers, wiring layers in the insulation layers, and via forming parts for interlayer connection, the via forming parts piercing the insulation layers. In the multilayer interconnection board, 0<L2?(L1/3) is set, where L1 denotes the distance between center positions of a pair of neighboring via forming parts formed in the same insulation layer and L2 denotes the shortest separation distance between the pair of the via forming parts.
    Type: Application
    Filed: November 22, 2006
    Publication date: January 24, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiteru Ochi, Nobutaka Itoh