Patents by Inventor Yoshiteru Ono
Yoshiteru Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10936279Abstract: A radio communication device is a radio communication device that performs radio communication by a press-to-talk communication system, and includes an operating unit that receives an operation of a user, an output unit that outputs a received voice signal as a voice, and a volume adjusting unit that adjusts a volume of the voice output by the output unit. The volume adjusting unit acquires source information that indicates a source of the voice signal when a predetermined operation by a user is made with respect to the operating unit, and adjusts the volume of the voice by using an adjustment coefficient that is a degree of adjustment of the volume of the voice, based on the acquired source information.Type: GrantFiled: December 18, 2019Date of Patent: March 2, 2021Assignee: JVCKENWOOD CorporationInventor: Yoshiteru Ono
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Publication number: 20200201595Abstract: A radio communication device is a radio communication device that performs radio communication by a press-to-talk communication system, and includes an operating unit that receives an operation of a user, an output unit that outputs a received voice signal as a voice, and a volume adjusting unit that adjusts a volume of the voice output by the output unit. The volume adjusting unit acquires source information that indicates a source of the voice signal when a predetermined operation by a user is made with respect to the operating unit, and adjusts the volume of the voice by using an adjustment coefficient that is a degree of adjustment of the volume of the voice, based on the acquired source information.Type: ApplicationFiled: December 18, 2019Publication date: June 25, 2020Inventor: Yoshiteru Ono
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Patent number: 7456701Abstract: A flexible substrate including: a first part provided with a first device DV1; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.Type: GrantFiled: March 10, 2005Date of Patent: November 25, 2008Assignee: Seiko Epson CorporationInventors: Keitaro Fujimori, Mihiro Nonoyama, Yukinari Shibata, Yoshiteru Ono, Hiroyasu Honda, Yoshiro Iwasa
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Publication number: 20050200413Abstract: A flexible substrate including: a first part provided with a first device DV1; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.Type: ApplicationFiled: March 10, 2005Publication date: September 15, 2005Inventors: Keitaro Fujimori, Mihiro Nonoyama, Yukinari Shibata, Yoshiteru Ono, Hiroyasu Honda, Yoshiro Iwasa
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Patent number: 6844576Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.Type: GrantFiled: August 30, 2002Date of Patent: January 18, 2005Assignee: Seiko Epson CorporationInventor: Yoshiteru Ono
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Publication number: 20040093576Abstract: A method for designing a semiconductor device includes receiving a net list of a semiconductor device, temporarily locating a plurality of functional blocks within a layout area of the semiconductor device and dividing a logic area of the semiconductor device into a plurality of rectangular areas and computing a predicted value of a utilization rate of the logic area and a predicted value of a wiring length of the semiconductor device based on a data base regarding a semiconductor device designed previously and the semiconductor device and the net list of the semiconductor device.Type: ApplicationFiled: July 30, 2003Publication date: May 13, 2004Applicant: SEIKO EPSON CORPORATIONInventors: Etsuko Terasawa, Yoshiteru Ono
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Patent number: 6720214Abstract: A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken lines) surrounded by a field insulating film on a semiconductor substrate for prototyping, and a prototype semiconductor integrated circuit is thereby manufactured, and then testing is performed. When the prototype semiconductor integrated circuit operates in a desired manner, impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines only) surrounded by a field insulating film on a semiconductor substrate for shipment, and a semiconductor integrated circuit for shipment is thereby manufactured.Type: GrantFiled: July 11, 2001Date of Patent: April 13, 2004Assignee: Seiko Epson CorporationInventor: Yoshiteru Ono
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Publication number: 20030006435Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.Type: ApplicationFiled: August 30, 2002Publication date: January 9, 2003Applicant: SEIKO EPSON CORPORATIONInventor: Yoshiteru Ono
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Patent number: 6476425Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.Type: GrantFiled: June 22, 2000Date of Patent: November 5, 2002Assignee: Seiko Epson CorporationInventor: Yoshiteru Ono
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Publication number: 20020048874Abstract: A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken lines) surrounded by a field insulating film on a semiconductor substrate for prototyping, and a prototype semiconductor integrated circuit is thereby manufactured, and then testing is performed. When the prototype semiconductor integrated circuit operates in a desired manner, impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines only) surrounded by a field insulating film on a semiconductor substrate for shipment, and a semiconductor integrated circuit for shipment is thereby manufactured.Type: ApplicationFiled: July 11, 2001Publication date: April 25, 2002Applicant: SEIKO EPSON CORPORATIONInventor: Yoshiteru Ono