Abstract: A shovel includes a lower traveling body, an upper turning body turnably attached to the lower traveling body, a boom pivotably attached to the upper turning body, an arm pivotably attached to the boom, an engine mounted on the upper turning body, a hydraulic pump mounted on the upper turning body, a fuel tank mounted on the upper turning body, a work walkway provided on an upper surface of the fuel tank for the movement of a worker, and a rollover valve provided at the top of the fuel tank at a position different from the work walkway.

Abstract: A shovel includes a lower traveling body, an upper turning body turnably attached to the lower traveling body, a boom pivotably attached to the upper turning body, an arm pivotably attached to the boom, an engine mounted on the upper turning body, a hydraulic pump mounted on the upper turning body, a fuel tank mounted on the upper turning body, a work walkway provided on an upper surface of the fuel tank for the movement of a worker, and a rollover valve provided at the top of the fuel tank at a position different from the work walkway.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: A power supply device includes: a first supply section that supplies power in accordance with an extent of a load in processing in a processing device by applying a voltage to the processing device which processes data; and a second supply section that supplies, to the processing device, power smaller than the supplying power by the first supply section, in accordance with an extent of a load in processing in the processing device to increase and decrease a voltage with respect to the application voltage by the first supply section.

Abstract: A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

Abstract: A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

Abstract: An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.

Abstract: A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.

Abstract: A signal generating apparatus includes: a direct digital synthesizer configured to generate an output signal of a frequency according to first control data based on a reference clock; and a controller configured to provide the direct digital synthesizer with the first control data at a timing synchronized with the reference clock, wherein the controller includes a table which stores second setting data for controlling the frequency of the output signal based on jitter information and provides the direct digital synthesizer with the second setting data in the table as the first control data at the timing.

Abstract: A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.

Abstract: A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit.

Abstract: A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.

Abstract: In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.

Abstract: In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.

Abstract: A power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero.

Abstract: A power circuit and method thereof are provided. The power circuit includes an output circuit having an alternating current-coupling element and that supplies an output signal of the output circuit to an amplifier as a driving voltage. The power circuit includes an envelope signal-extracting unit extracting an envelope signal from a carrier wave, a simulation signal-waveform generating unit generating a simulation signal including a fluctuation component occurring when the envelope signal is transmitted to the output circuit, a fluctuation component-extracting unit extracting the fluctuation component included in the simulation signal, and an inverted component-generating unit generating an inverted component obtained by performing phase inversion for the fluctuation component, where the fluctuation component occurring in the output circuit is canceled out through the inverted component.

Abstract: A power supply device of the invention includes: a supply section that supplies power to a second processing device which processes data in response to processing execution by a first processing device which processes data; a load detection section that detects a load of processing execution by the first processing device; and a power control section that causes the supply section to increase or decrease power supply according to the magnitude of load detected by the load detection section. The load of processing execution by the first processing device disposed in the upstream side relative to the second processing device is detected, and power supply to the second processing device is increased or decreased according to the detected magnitude of load. Accordingly, even when the amount of processing data sharply increases, sufficient power can be unfailingly supplied to the second processing device.

Abstract: A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.

Abstract: An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.