Patents by Inventor Yoshito Nakase

Yoshito Nakase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050181527
    Abstract: A method for forming scribed grooves on a wafer and an apparatus for implementing the method. The method moves the cutting part such that its cutting edge forms an inverted trapezoid-shaped path, thereby reducing the scribing angle of the cutting edge to an acute angle. Consequently, the stress produced by the mechanical shock at the time of the scribing can be dispersed in the moving direction of the cutting edge and in a direction perpendicular to the surface of the wafer. The horizontal movement of the scribing cutting edge in the wafer enables the application of a sufficient load in a direction perpendicular to the scribing plane in the wafer. Consequently, vertical cracks are sufficiently generated, and the amount of dimensional deviation between the scribed groove and the cleaved plane is reduced. This method can produce chips featuring outside dimensions with higher precision and cleaved surfaces with high-quality mirror finish.
    Type: Application
    Filed: March 16, 2005
    Publication date: August 18, 2005
    Inventors: Yuji Ohno, Hiroshi Imai, Yoshito Nakase
  • Patent number: 6916726
    Abstract: A method for forming scribed grooves on a wafer and an apparatus for implementing the method. The method moves the cutting part such that its cutting edge forms an inverted trapezoid-shaped path, thereby reducing the scribing angle of the cutting edge to an acute angle. Consequently, the stress produced by the mechanical shock at the time of the scribing can be dispersed in the moving direction of the cutting edge and in a direction perpendicular to the surface of the wafer. The horizontal movement of the scribing cutting edge in the wafer enables the application of a sufficient load in a direction perpendicular to the scribing plane in the wafer. Consequently, vertical cracks are sufficiently generated, and the amount of dimensional deviation between the scribed groove and the cleaved plane is reduced. This method can produce chips featuring outside dimensions with higher precision and cleaved surfaces with high-quality mirror finish.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: July 12, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuji Ohno, Hiroshi Imai, Yoshito Nakase
  • Publication number: 20040126995
    Abstract: A method for forming scribed grooves on a wafer and an apparatus for implementing the method. The method moves the cutting part such that its cutting edge forms an inverted trapezoid-shaped path, thereby reducing the scribing angle of the cutting edge to an acute angle. Consequently, the stress produced by the mechanical shock at the time of the scribing can be dispersed in the moving direction of the cutting edge and in a direction perpendicular to the surface of the wafer. The horizontal movement of the scribing cutting edge in the wafer enables the application of a sufficient load in a direction perpendicular to the scribing plane in the wafer. Consequently, vertical cracks are sufficiently generated, and the amount of dimensional deviation between the scribed groove and the cleaved plane is reduced. This method can produce chips featuring outside dimensions with higher precision and cleaved surfaces with high-quality mirror finish.
    Type: Application
    Filed: July 22, 2003
    Publication date: July 1, 2004
    Inventors: Yuji Ohno, Hiroshi Imai, Yoshito Nakase