Abstract: In a first-in-first-out register device positioned intermediately between an address calculation circuit and an operation execution circuit, both of which are individually operable in pipeline fashions, a stage number is varied from one to another in a register unit having a plurality of register stages, in consideration of an execution time which is necessary for a bus access operation carried out in response to a read instruction and which is variable. A maximum usable stage number is determined by a pointer control circuit in response to the variable execution time and is compared with an actual stage number, which is sent from a detector and which indicates an actual stage of the register unit. As a result, the register unit is controlled, so that the actual stage does not exceed the maximum usable stage.