Abstract: A secondary battery system including plural batteries, extends the lifetime of each battery, and improves the charge/discharge (energy) efficiency of a whole system is provided. A secondary battery system includes plural batteries individually controllable for charging/discharging, plural PCSs each connected to the corresponding battery and performing charging/discharging to the connected battery, and a battery controller distributing a charge/discharge power value as a whole system to each of the PCSs at a fixed cycle or an arbitrary timing. The battery controller includes a preference order calculator setting a preference order to the plural batteries at each time point based on a deterioration characteristic of each battery related to each SOC thereof, and a distribution rate determining unit distributing the charge/discharge power value to the PCSs in accordance with the preference order.

Abstract: An information processing device in an embodiment includes a storage and an operation curve generator. The storage stores therein linear data including a slope and a curve for each set of certain locations, and train data including an acceleration-deceleration characteristic. The operation curve generator sets a plurality of deceleration section candidates on the basis of the linear data about the set of certain locations stored in the storage, obtains, for each of the deceleration section candidates, a change rate of energy consumption when the deceleration is performed by a certain speed using a preset operation curve, the linear data, and the train data, selects the section in which the change rate of energy consumption in the obtained change rates of energy consumption is the largest from the deceleration section candidates, and updates the preset operation curve utilizing the selected deceleration section and the certain speed.

Abstract: A secondary battery system including plural batteries, extends the lifetime of each battery, and improves the charge/discharge (energy) efficiency of a whole system is provided. A secondary battery system includes plural batteries individually controllable for charging/discharging, plural PCSs each connected to the corresponding battery and performing charging/discharging to the connected battery, and a battery controller distributing a charge/discharge power value as a whole system to each of the PCSs at a fixed cycle or an arbitrary timing. The battery controller includes a preference order calculator setting a preference order to the plural batteries at each time point based on a deterioration characteristic of each battery related to each SOC thereof, and a distribution rate determining unit distributing the charge/discharge power value to the PCSs in accordance with the preference order.

Abstract: Provided is a programmable control apparatus for performing a self-diagnosis process using a short-period single loop. The programmable control apparatus includes: a signal processing unit configured to sequentially process inputted external signals based on a program in a memory; a data acquisition unit configured to acquire data from a specified nth block of a plurality of blocks obtained by dividing an area of the memory; a diagnostic unit configured to diagnose health of the nth block based on the acquired data and then prompt a next external signal to be processed; and a block specification unit configured to cause health of an (n+1)th block to be diagnosed after the next external signal is processed.

Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

Abstract: In a digital control device, when a normal mode for carrying out a normal process is selected by a mode switch, a computation unit transfers base process code and APL process code which controls the normal process from a code storage device to a main memory, loads the base process code and the APL process code which are transferred to the main memory, and carries out the normal process. When a test mode for carrying out a test process is selected by the mode switch, the computation unit transfers the base process code and test process code which controls the test process from the code storage device to the main memory, loads the base process code and the test process code which are transferred to the main memory, and carries out the test process.

Abstract: The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.

Abstract: In a watt-hour meter, encoders 116, 117, 118 and 119 respectively convert a signal concerning a current and voltage used by a customer into a code sequence signal by Reed-Solomon codes or convolutional codes. Decoders 121, 122, 123, and 124 reversely convert the code sequence signal to the signal concerning the current and voltage. A power calculating section 125 converts the signal concerning the current and voltage into data concerning electricity consumption.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: A control device includes a diagnostic pulse signal generating section having an internal circuit that generates control data and generates diagnostic pulse data for diagnosing the operating terminal and diagnoses the function of the signal line and the operating terminal from the waveform of a feedback signal of the diagnostic pulse signal; a variable amplification circuit that multiplexes the diagnostic pulse signal on the control signal and sends the result to the operating terminal with a preset signal level; and a receiving circuit that receives the feedback signal and sends it to the internal circuit. The internal circuit comprises a correction pulse data generating section that corrects the diagnostic pulse data by correcting the rise time of the diagnostic pulse signal. Even if the length of the signal line is long, the diagnostic pulse signal reception can be achieved without expanding the pulse width of the diagnostic pulse signal.

Abstract: A processor includes a computation unit; a storage unit storing a program; and a data transmission circuit that transmits to an operation monitoring unit a signal corresponding to an instruction for reporting the execution stage of the program. The operation monitoring unit: includes a transition operation identification. circuit and a loop processing identification circuit. The transition operation identification circuit receives a start ID instruction with an attached ID that identifies a task; a termination ID instruction that identifies termination of task operation; and if the task is execution of loop processing, a loop instruction that reports the maximum value of the number of times of this loop processing. The transition operation identification circuit identifies success of the transition operations of the tasks of the program, based on the ID instructions. The loop processing identification circuit identifies abnormality of the number of times of loop processing.

Abstract: A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.

Abstract: A gas appliance judgment apparatus and method by which a type of gas appliance in use and the existence of a gas leak can be identified. In operation, noise is removed from measured instantaneous flow volume, whereupon the “length”, “initial flow volume” and “sequence of transited regions” of the variable portion of the flow volume and the “length”, “average value” and “gradient” of the flat portion of the flow volume are extracted. A rule having characteristics data which matches the characteristics of the variable portion and the flat portion of the flow volume is then searched, and points are added respectively for the type of gas appliance and for the existence of a gas leak. When the added points are not less than a previously established threshold value, then the type of gas appliance in use is determined, and appliance type information is output as a judgment result.

Abstract: A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

Abstract: The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.

Abstract: A gas appliance judgment apparatus and method by which a type of gas appliance in use and the existence of a gas leak can be identified. In operation, noise is removed from measured instantaneous flow volume, whereupon the “length”, “initial flow volume” and “sequence of transited regions” of the variable portion of the flow volume and the “length”, “average value” and “gradient” of the flat portion of the flow volume are extracted. A rule having characteristics data which matches the characteristics of the variable portion and the flat portion of the flow volume is then searched, and points are added respectively for the type of gas appliance and for the existence of a gas leak. When the added points are not less than a previously established threshold value, then the type of gas appliance in use is determined, and appliance type information is output as a judgment result.

Abstract: According to the present invention, mistaken detection of a gas leak can be prevented even when using an appliance which has been newly installed in a dwelling receiving a gas supply, and whereby a gas leak can be detected rapidly, efficiently and accurately. The characteristics extraction means 5 extracts characteristics of a gas flow including a combination of the instantaneous flow volume data and the instantaneous flow volume time differential value, on the basis of the data obtained by the flow volume measurement means 1, pressure measurement means 2, instantaneous flow volume time differential operation means 3 and pressure time differential operation means 4.

Abstract: A gas appliance judgment apparatus and method by which a type of gas appliance in use and the existence of a gas leak can be identified. In operation, noise is removed from measured instantaneous flow volume, whereupon the “length”, “initial flow volume” and “sequence of transited regions” of the variable portion of the flow volume and the “length”, “average value” and “gradient” of the flat portion of the flow volume are extracted. A rule having characteristics data which matches the characteristics of the variable portion and the flat portion of the flow volume is then searched, and points are added respectively for the type of gas appliance and for the existence of a gas leak. When the added points are not less than a previously established threshold value, then the type of gas appliance in use is determined, and appliance type information is output as a judgment result.