Abstract: Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value.

Abstract: A first mixer generates a first and a second clock signal having a phase opposite to that of the first clock signal. A second mixer generates a third clock signal having a phase lead angle of 90 degrees with respect to the first clock signal and a fourth clock signal having a phase opposite to that of the third clock signal. An ADC generates a digital signal from a signal that is generated on the basis of a composite signal of a voltage signal formed on the basis of the exclusive OR of the first and the third clock signal and a voltage signal formed on the basis of the exclusive OR of the second and the fourth clock signal. An adder adds the digital signal to the first control signal to generate the second control signal and supplies the second control signal to the second mixer.

Abstract: A first mixer generates a first and a second clock signal having a phase opposite to that of the first clock signal. A second mixer generates a third clock signal having a phase lead angle of 90 degrees with respect to the first clock signal and a fourth clock signal having a phase opposite to that of the third clock signal. An ADC generates a digital signal from a signal that is generated on the basis of a composite signal of a voltage signal formed on the basis of the exclusive OR of the first and the third clock signal and a voltage signal formed on the basis of the exclusive OR of the second and the fourth clock signal. An adder adds the digital signal to the first control signal to generate the second control signal and supplies the second control signal to the second mixer.

Abstract: Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value.

Abstract: The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.

Abstract: The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.

Abstract: An apparatus measures a voltage fluctuation waveform in a semiconductor integrated circuit having a large number of wiring layers and being operated on a lower voltage without a destructive inspection. For this propose, the apparatus includes a power-source-system waveform converting circuit, disposed close to a functional circuit and in the LSI and operated on a second rated voltage higher than a first rated voltage, for converting the voltage fluctuation waveform of the power source system into an electrical current waveform; a pad for outputting the electric current waveform outside the LSI; and a wiring, arranged in the LSI, for connecting the power-source-system waveform converting circuit and the pad. The apparatus is used to measure a voltage fluctuation waveform near a particular circuit in operation included in, for example, a CMOS LSI.

Abstract: An apparatus measures a voltage fluctuation waveform in a semiconductor integrated circuit having a large number of wiring layers and being operated on a lower voltage without a destructive inspection. For this propose, the apparatus includes a power-source-system waveform converting circuit, disposed close to a functional circuit and in the LSI and operated on a second rated voltage higher than a first rated voltage, for converting the voltage fluctuation waveform of the power source system into an electrical current waveform; a pad for outputting the electric current waveform outside the LSI; and a wiring, arranged in the LSI, for connecting the power-source-system waveform converting circuit and the pad. The apparatus is used to measure a voltage fluctuation waveform near a particular circuit in operation included in, for example, a CMOS LSI.

Abstract: A power-on reset signal preparing circuit including a pulse width preparing circuit for generating a pulse for resetting a main circuit based on a driving voltage output from a driving circuit based on the output voltages from two charging circuits with different charging times. The driving circuit may be a switching circuit utilizing charged potential difference of the two charging circuits, a gate circuit utilizing a charging time difference of the two charging circuits, or a differential transistor pair utilizing the charging potential difference or time difference of the two charging circuits. The pulse width preparing circuit may be formed by two wiring lines, connected between the output of the driving circuit and the ground and running substantially parallel to each other, whereby the capacitors may be small in size.

Abstract: A power-on reset signal preparing circuit comprises a pulse width preparing circuit (19) for generating a pulse for resetting a main circuit (20) based on a driving voltage output from a driving circuit (17, 41, 61, 62) based on the output voltages from two charging circuits (13, 16) with different charging times. The driving circuit may be a switching means (17) utilizing charged potential difference of the two charging circuits, a gate means utilizing a charging time difference of the two charging circuits, or a differential transistor pair (61, 62) utilizing the charging potential difference or time difference of the two charging circuits. The pulse width preparing circuit (19) may be formed by two wiring lines (32, 33), connected between the output of the driving circuit and the ground and running substantially parallel to each other, whereby the capacitors may be small in size.