Abstract: An extractor of a square root has rows of first and second arithmetic elements, the number of which is determined in correspondence with bit lengths of a number to be extracted and of the square root thereof. The first arithmetic element comprises an adder for carrying out an addition operation based on either bit data out of the number to be extracted or zero, inverted input data, and carry data, to output addition result data and carry data, first selection circuit for outputting as first output data either the addition result data, or either the bit data or zero, based on selection data, and a second selection circuit for selecting either one or zero based on the selection data to output the selected data as second output data.

Abstract: A circuit apparatus for detecting a preceding value "1" has a preceding value "1" detecting circuit for dividing detected data constructed by plural bits into blocks every plural bits from an upper bit side, the preceding value "1" detecting circuit detecting the preceding value "1" by bit data supplied every divided block and a detecting signal indicative of value "1"; and a value "1" detecting signal transmitting circuit for detecting whether all the bit data supplied to the preceding value "1" detecting circuit at the preceding stage show value "0" or not, the value "1" detecting signal transmitting circuit transmitting the detecting signal indicative of value "1" as a basis of the detection of the preceding value "1" to the preceding value "1" detecting circuit at the next stage on the basis of detected results.

Abstract: An incrementer circuit includes a plurality of input terminals for receiving an address data, having a plurality of bits, to be incremented, a carry signal generating unit for generating a carry signal for each bit of the address data and a plurality of output terminals where an incremented address data appears. The carry signal generating unit includes a detector for detecting whether or not all of a predetermined number of less significant bits of the address data are at high level and outputs a detection signal if so. In response to this detection signal, a carry signal is generated and supplied to a bit which is more significant than the most significant bit of the predetermined number of less significant bits by one bit.