Patents by Inventor Yoshitsugu Tanaka

Yoshitsugu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11635870
    Abstract: To achieve the object of making it easier to collectively grasp the state of the production line, an information processing method includes a first screen displaying step and a second screen displaying step. A first screen displaying step displays a first screen including a plurality of widgets. Each of the widgets is configured based on information outputted from application software which is associated with each of the widgets among a plurality of pieces of application software that manage a state of a production line. A second screen displaying step, when an operation performed on any widget of the plurality of widgets has been accepted, displays a second screen of application software which is associated with the widget.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 25, 2023
    Assignee: SINTOKOGIO, LTD.
    Inventors: Narihiro Akatsuka, Yoshitsugu Tanaka, Naohisa Nakamura
  • Publication number: 20230029242
    Abstract: A screen image generation device for generating a screen image indicating a state of a facility in a production plant is provided which ensures a real-time property of a management screen image needed in actual production plants and reduce required levels of making a network faster in speed and wider in bandwidth. A server functioning as the device performs first acquisition of regularly acquiring first data transmitted from a sensor and concerning the facility at intervals of a first time, second acquisition of regularly acquiring second data transmitted from a controller and concerning the facility at intervals of a second time shorter than the first time, third acquisition of acquiring, in real time, an alert irregularly transmitted from the controller and concerning the facility, and generation of generating the management screen image indicating the state of the facility in accordance with the first data, the second data, and the alert.
    Type: Application
    Filed: June 6, 2022
    Publication date: January 26, 2023
    Applicant: SINTOKOGIO, LTD.
    Inventors: Narihiro AKATSUKA, Naohisa NAKAMURA, Yoshitsugu TANAKA
  • Publication number: 20220147037
    Abstract: To achieve the object of making it easier to collectively grasp the state of the production line, an information processing method includes a first screen displaying step and a second screen displaying step. A first screen displaying step displays a first screen including a plurality of widgets. Each of the widgets is configured based on information outputted from application software which is associated with each of the widgets among a plurality of pieces of application software that manage a state of a production line. A second screen displaying step, when an operation performed on any widget of the plurality of widgets has been accepted, displays a second screen of application software which is associated with the widget.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 12, 2022
    Applicant: SINTOKOGIO, LTD.
    Inventors: Narihiro AKATSUKA, Yoshitsugu TANAKA, Naohisa NAKAMURA
  • Patent number: 8785334
    Abstract: A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yoshitsugu Tanaka
  • Patent number: 8741786
    Abstract: A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Koji Akiyama, Hirokazu Higashijima, Yoshitsugu Tanaka, Yasushi Akasaka, Koji Yamashita
  • Patent number: 8570825
    Abstract: A disclosed temperature sensor includes a charge trap structure including a silicon oxide film formed on a substrate; an aluminum oxide film that is formed on the silicon oxide film, wherein oxygen is injected into the aluminum oxide film from an upper surface thereof; and an electrode formed on the aluminum oxide film, wherein a flat band voltage of the charge trap structure is temperature dependent.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshitsugu Tanaka
  • Publication number: 20120309207
    Abstract: A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.
    Type: Application
    Filed: May 17, 2012
    Publication date: December 6, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Koji AKIYAMA, Hirokazu Higashijima, Yoshitsugu Tanaka, Yasushi Akasaka, Koji Yamashita
  • Publication number: 20120299085
    Abstract: A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 29, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Yoshitsugu TANAKA
  • Publication number: 20120176835
    Abstract: A disclosed temperature sensor includes a charge trap structure including a silicon oxide film formed on a substrate; an aluminum oxide film that is formed on the silicon oxide film, wherein oxygen is injected into the aluminum oxide film from an upper surface thereof; and an electrode formed on the aluminum oxide film, wherein a flat band voltage of the charge trap structure is temperature dependent.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 12, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Yoshitsugu TANAKA
  • Patent number: 7955922
    Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r1 of the sacrificial oxide film is higher than an etching rate r2 of the buried oxide layer during the etching.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hajime Nakabayashi, Takuya Sugawara, Takashi Kobayashi, Junichi Kitagawa, Yoshitsugu Tanaka
  • Publication number: 20080171407
    Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r1 of the sacrificial oxide film is higher than an etching rate r2 of the buried oxide layer during the etching.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 17, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hajime Nakabayashi, Takuya Sugawara, Takashi Kobayashi, Junichi Kitagawa, Yoshitsugu Tanaka
  • Patent number: 6634370
    Abstract: Liquid treatment units are disposed in multi-tiers surrounding a main-arm 35. Among liquid treatment units, plating units M1 through M4 are disposed on a lower tier side, and a unit for post-treatment process such as a cleaning unit 70 where a cleaner atmosphere is necessary is disposed on an upper tier side. Thereby, an improvement in an area efficiency and the formation and maintenance of a clean atmosphere can be simultaneously obtained.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: October 21, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Satoshi Nakashima, Wataru Okase, Takenobu Matsuo, Tameyasu Hyakuzuka, Yasushi Yagi, Yoshiyuki Harima, Jun Yamauchi, Hiroki Taniyama, Kyungho Park, Yoshitsugu Tanaka, Yoshinori Kato, Hiroshi Sato
  • Patent number: 6565662
    Abstract: A plasma etching apparatus includes a process container formed of a container main body and an upper casing combined with each other. A detaching device is provided to move the upper casing between a mounted position where the upper casing is put on the container main body, and a retreated position where the upper casing is removed from the container main body. The detaching device supports the upper casing to be rotatable, movable up and down, and movable in a lateral direction, relative to the container main body. The retreated position is arranged such that the upper casing does not interfere with the container main body when the upper casing is rotated there.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: May 20, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Amano, Yoshitsugu Tanaka
  • Publication number: 20010037764
    Abstract: Liquid treatment units are disposed in multi-tiers surrounding a main-arm 35. Among liquid treatment units, plating units M1 through M4 are disposed on a lower tier side, and a unit for post-treatment process such as a cleaning unit 70 where a cleaner atmosphere is necessary is disposed on an upper tier side. Thereby, an improvement in an area efficiency and the formation and maintenance of a clean atmosphere can be simultaneously obtained.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 8, 2001
    Inventors: Satoshi Nakashima, Wataru Okase, Takenobu Matsuo, Tameyasu Hyakuzuka, Yasushi Yagi, Yoshiyuki Harima, Jun Yamauchi, Hiroki Taniyama, Kyungho Park, Yoshitsugu Tanaka, Yoshinori Kato, Hiroshi Sato
  • Publication number: 20010006094
    Abstract: A plasma etching apparatus includes a process container formed of a container main body and an upper casing combined with each other. A detaching device is provided to move the upper casing between a mounted position where the upper casing is put on the container main body, and a retreated position where the upper casing is removed from the container main body. The detaching device supports the upper casing to be rotatable, movable up and down, and movable in a lateral direction, relative to the container main body. The retreated position is arranged such that the upper casing does not interfere with the container main body when the upper casing is rotated there.
    Type: Application
    Filed: December 20, 2000
    Publication date: July 5, 2001
    Inventors: Kenji Amano, Yoshitsugu Tanaka
  • Patent number: 4486108
    Abstract: A semi-automatic paper insertion apparatus for a printer, a typewriter, etc. comprising a first condition in which the paper bail is out of engagement with the platen and the paper feed drive source is actuated and a second condition in which the paper bail is in engagement with the platen and the paper feed drive source is actuated, comprises further a third condition in which the paper bail is out of engagement with the platen and the paper feed drive source is deactuated, whereby a skew correcting operation can be performed without any trouble.
    Type: Grant
    Filed: November 5, 1981
    Date of Patent: December 4, 1984
    Assignee: Ricoh Company Ltd.
    Inventor: Yoshitsugu Tanaka