Patents by Inventor Yoshiya Moriyama
Yoshiya Moriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10164017Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.Type: GrantFiled: February 2, 2018Date of Patent: December 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
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Publication number: 20180158911Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.Type: ApplicationFiled: February 2, 2018Publication date: June 7, 2018Inventors: Yuichiro SASAKI, Bong Soo KIM, Tae Gon KIM, Yoshiya MORIYAMA, Seung Hyun SONG, Alexander SCHMIDT, Abraham YOO, Heung Soon LEE, Kyung In CHOI
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Patent number: 9911809Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.Type: GrantFiled: February 3, 2017Date of Patent: March 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
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Publication number: 20170373151Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.Type: ApplicationFiled: February 3, 2017Publication date: December 28, 2017Inventors: Yuichiro SASAKI, Bong Soo KIM, Tae Gon KIM, Yoshiya MORIYAMA, Seung Hyun SONG, Alexander SCHMIDT, Abraham YOO, Heung Soon LEE, Kyung In CHOI
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Patent number: 9647038Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: GrantFiled: June 28, 2016Date of Patent: May 9, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiya Moriyama, Hiromasa Fujimoto, Kosaku Saeki, Nobuyoshi Takahashi
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Publication number: 20160307967Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Kosaku SAEKI, Nobuyoshi TAKAHASHI
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Patent number: 9406722Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: GrantFiled: November 25, 2014Date of Patent: August 2, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiya Moriyama, Hiromasa Fujimoto, Kosaku Saeki, Nobuyoshi Takahashi
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Publication number: 20150076484Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Kosaku SAEKI, Nobuyoshi TAKAHASHI
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Patent number: 8809965Abstract: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes first offset sidewalls formed on side surfaces in a gate width direction of a first gate electrode, second offset sidewalls formed on side surfaces in a gate length direction and the side surfaces of the gate width direction of the first gate electrode with the first offset sidewalls being interposed between the second offset sidewalls and the first gate electrode, and first extension regions. The second MIS transistor includes third offset sidewalls formed on side surfaces in a gate length direction and a gate width direction of a second gate electrode, fourth offset sidewalls formed on the side surfaces in the gate length and width directions of the second gate electrode with the third offset sidewalls being interposed between the fourth offset sidewalls and the second gate electrode, and second extension regions.Type: GrantFiled: October 31, 2012Date of Patent: August 19, 2014Assignee: Panasonic CorporationInventor: Yoshiya Moriyama
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Patent number: 8796779Abstract: A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.Type: GrantFiled: October 31, 2012Date of Patent: August 5, 2014Assignee: Panasonic CorporationInventors: Satoru Ito, Yoshiya Moriyama, Hiroshi Ohkawa, Susumu Akamatsu
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Patent number: 8779524Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5s.Type: GrantFiled: July 20, 2012Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Yoshiya Moriyama, Hiromasa Fujimoto, Satoru Itou, Susumu Akamatsu, Hiroshi Ohkawa
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Patent number: 8766335Abstract: A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx>n is satisfied.Type: GrantFiled: October 31, 2012Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventor: Yoshiya Moriyama
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Publication number: 20120280328Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5 s.Type: ApplicationFiled: July 20, 2012Publication date: November 8, 2012Applicant: Panasonic CorporationInventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Satoru ITOU, Susumu AKAMATSU, Hiroshi OHKAWA
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Publication number: 20090114998Abstract: A first MIS transistor is formed in a low voltage transistor formation region and includes a gate insulating film and a first gate electrode composed of a metal film and a polycrystalline silicon film. A second MIS transistor is formed in a high voltage transistor formation region and includes a gate insulating film and a second gate electrode composed of a polycrystalline silicon film. An equivalent oxide thickness of the gate insulating film formed in the low voltage transistor formation region is thinner than an equivalent oxide thickness of the gate insulating film formed in the high voltage transistor formation region. A level of the surface of a semiconductor substrate in the low voltage transistor formation region is higher than a level of the surface of a semiconductor substrate in the high voltage transistor formation region.Type: ApplicationFiled: October 30, 2008Publication date: May 7, 2009Inventor: Yoshiya MORIYAMA
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Patent number: 7474548Abstract: A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.Type: GrantFiled: December 13, 2006Date of Patent: January 6, 2009Assignee: Panasonic CorporationInventors: Yoshiya Moriyama, Yuji Harada, Keita Takahashi
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Patent number: 7439577Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.Type: GrantFiled: July 31, 2006Date of Patent: October 21, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
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Publication number: 20070152265Abstract: A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.Type: ApplicationFiled: December 13, 2006Publication date: July 5, 2007Inventors: Yoshiya Moriyama, Yuji Harada, Keita Takahashi
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Publication number: 20070108509Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.Type: ApplicationFiled: July 31, 2006Publication date: May 17, 2007Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
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Publication number: 20030011419Abstract: A semiconductor integrated circuit device is a voltage boosting circuit for amplifying a voltage inputted thereto and outputting the amplified voltage and has a plurality of capacitors and a plurality of intrinsic MIS transistors. Of the plurality of MIS transistors, at least one has a gate length different from the respective gate lengths of the other MIS transistors.Type: ApplicationFiled: June 12, 2002Publication date: January 16, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma,Inventor: Yoshiya Moriyama