Patents by Inventor Yoshiyasu Futamura

Yoshiyasu Futamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10648886
    Abstract: In adjustment processing executed at the same period as waveform analysis processing, a CPU of a microcomputer permits an execution of the waveform analysis processing on condition that the waveform analysis processing has been completed. Thus a period of non-execution of the waveform analysis processing is ensured between a completion of preceding waveform analysis processing to an execution of next waveform analysis processing. Since low priority processing, which has been disabled to be executed, is enabled to be executed, it is possible to stop continuation of disablement of execution of the low priority processing.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 12, 2020
    Assignee: DENSO CORPORATION
    Inventors: Tomofumi Yoshida, Yoshiyasu Futamura, Shinya Noda
  • Publication number: 20180372587
    Abstract: In adjustment processing executed at the same period as waveform analysis processing, a CPU of a microcomputer permits an execution of the waveform analysis processing on condition that the waveform analysis processing has been completed. Thus a period of non-execution of the waveform analysis processing is ensured between a completion of preceding waveform analysis processing to an execution of next waveform analysis processing. Since low priority processing, which has been disabled to be executed, is enabled to be executed, it is possible to stop continuation of disablement of execution of the low priority processing.
    Type: Application
    Filed: February 23, 2018
    Publication date: December 27, 2018
    Inventors: Tomofumi YOSHIDA, Yoshiyasu FUTAMURA, Shinya NODA
  • Patent number: 8315778
    Abstract: A first judgment circuit and a second judgment circuit are adapted to set a judging signal high when a judgment data sent from a microprocessor indicates failure. The high level judging signal triggers a forced idle command connected to a motor driver, to be high level whereby the motor is forcibly suspended. Subsequently, when a reset command is accidentally transmitted by the microprocessor due to an unexpected fault, a first judging signal from the first judgment circuit is reset to low level. However, a second judging signal from the second judgment circuit remains high level. As a result, the forced idle command stays high level.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: November 20, 2012
    Assignee: Denso Corporation
    Inventors: Toshio Nishimura, Hirotaka Kunibe, Yoshiyasu Futamura, Shoukichi Hosoe, Hirokazu Tsuji, Akira Ito, Tokutada Takahashi, Takamasa Oguri
  • Publication number: 20110153180
    Abstract: A first judgment circuit and a second judgment circuit are adapted to set a judging signal high when a judgment data sent from a microprocessor indicates failure. The high level judging signal triggers a forced idle command connected to a motor driver, to be high level whereby the motor is forcibly suspended. Subsequently, when a reset command is accidentally transmitted by the microprocessor due to an unexpected fault, a first judging signal from the first judgment circuit is reset to low level. However, a second judging signal from the second judgment circuit remains high level. As a result, the forced idle command stays high level.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: DENSO CORPORATION
    Inventors: Toshio NISHIMURA, Hirotaka Kunibe, Yoshiyasu Futamura, Shoukichi Hosoe, Hirokazu Tsuji, Akira Ito, Tokutada Takahashi, Takamasa Oguri