Patents by Inventor Yoshiyuki Fukami

Yoshiyuki Fukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220257874
    Abstract: A blood vessel specifying device (1) includes an image processing device (31) configured to subject an image for analysis of a target part (2) to image processing to acquire blood vessel information including positions and shapes of blood vessels included in the target part (2), an evaluation device (32) configured to use the blood vessel information to assign a point rating regarding a parameter that indicates a conformity to a particular purpose with respect to the blood vessels included in the image for analysis depending on a degree of the conformity, and a specification device (33) configured to specify conforming blood vessels conforming to the purpose from the blood vessels included in the target part (2) in accordance with rating points of the parameter.
    Type: Application
    Filed: February 28, 2020
    Publication date: August 18, 2022
    Inventors: Yuki SAITO, Yoshiyuki FUKAMI, Hiroshi KAMIYA, Osamu ARAI, Kazuhiko SASAGAWA, Koichi SAGAWA, Yasutaka HANADA, Toshiro ONO
  • Publication number: 20220249016
    Abstract: A blood vessel position display device (1) includes an image processing device (31) configured to subject an image for analysis of a target part (2) to image processing to acquire blood vessel information including positions and shapes of blood vessels included in the target part (2), a selection device (32) configured to choose blood vessels as conforming blood vessels in which a parameter obtained from the blood vessel information satisfies specific conditions, an image generation device (33) configured to generate a projection image including display lines at least set to have lengths corresponding to the conforming blood vessels, and a projection device (40) configured to cause the positions of the display lines to correspond to the positions of the conforming blood vessels so as to project the projection image on the target part (2).
    Type: Application
    Filed: February 28, 2020
    Publication date: August 11, 2022
    Inventors: Yuki SAITO, Yoshiyuki FUKAMI, Hiroshi KAMIYA, Osamu ARAI, Kazuhiko SASAGAWA, Koichi SAGAWA, Yasutaka HANADA, Toshiro ONO
  • Publication number: 20220149549
    Abstract: [Problem] To provide an electrical connecting apparatus that can realize a stable electrical connecting property by expanding a contact area between an electrode region of a wiring substrate and a connector as compared to the prior art, and suppressing contact resistance.
    Type: Application
    Filed: December 13, 2019
    Publication date: May 12, 2022
    Inventors: Shou HARAKO, Noboru OTABE, Hiroshi KAMIYA, Yoshiyuki FUKAMI, Shogo MIZUTANI
  • Patent number: 11099227
    Abstract: Included are an insulating plate 41 including a plurality of insulating synthetic resin layers, wiring circuits 44a, 44b, and 44c provided in the insulating plate 41, a thin-film resistor 46 formed to be buried in the insulating plate 41 and electrically connected to the wiring circuits 44a, 44b, and 44c, a heat dissipating portion 47 provided over one surface of the insulating plate to be opposed to the thin-film resistor 46 via a part of the plurality of insulating synthetic resin layers and having higher heat conductivity than that of the insulating plate 41, a pedestal portion 48 formed to be buried in the insulating plate 41 and provided to be opposed to the thin-film resistor 46 via a part of the plurality of insulating synthetic resin layers on an opposite side of the heat dissipating portion 47 and having higher heat conductivity than that of the insulating plate 41, and a heat dissipation and pedestal connecting portion 49 connecting the heat dissipating portion 47 to the pedestal portion 48 and havi
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 24, 2021
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Noboru Otabe, Yoshiyuki Fukami
  • Patent number: 10989738
    Abstract: To reduce inspection time by changing an action speed of a movable axis movable part while considering size information of an electrode terminal as a contact destination of a probe. An inspection apparatus of the present disclosure is an inspection apparatus with a plurality of movable probes that brings each of the movable probes into contact with each of a plurality of objects to be inspected on a board to be inspected so as to measure electrical characteristics between the objects to be inspected.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 27, 2021
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventor: Yoshiyuki Fukami
  • Publication number: 20200400739
    Abstract: Included are an insulating plate 41 including a plurality of insulating synthetic resin layers, wiring circuits 44a, 44b, and 44c provided in the insulating plate 41, a thin-film resistor 46 formed to be buried in the insulating plate 41 and electrically connected to the wiring circuits 44a, 44b, and 44c, a heat dissipating portion 47 provided over one surface of the insulating plate to be opposed to the thin-film resistor 46 via a part of the plurality of insulating synthetic resin layers and having higher heat conductivity than that of the insulating plate 41, a pedestal portion 48 formed to be buried in the insulating plate 41 and provided to be opposed to the thin-film resistor 46 via a part of the plurality of insulating synthetic resin layers on an opposite side of the heat dissipating portion 47 and having higher heat conductivity than that of the insulating plate 41, and a heat dissipation and pedestal connecting portion 49 connecting the heat dissipating portion 47 to the pedestal portion 48 and havi
    Type: Application
    Filed: April 6, 2017
    Publication date: December 24, 2020
    Inventors: Noboru OTABE, Yoshiyuki FUKAMI
  • Patent number: 10705122
    Abstract: Provided is a probe card with which the adjustment of height deviations of needle tip parts of probes and the adjustment of parallelism between the probes and an object to be inspected are simplified. The probe card 1 has: a wiring substrate 2 having wiring 4 therein or on a surface thereof or the like; a plurality of probes 3; and a dielectric film 6. The dielectric film 6 is disposed to be spaced a distance away from a main surface 8 of the wiring substrate 2 at a position spaced away further from the wiring substrate 2 than the needle tip parts 13 of the probes 3, so that one surface 21 of the dielectric film 6 faces the needle tip parts 13 and faces the main surface 8 that is a probe installation surface of the wiring substrate 2. The probe card 1 configures a state in which the needle tip parts 13 face an electrode of an object to be inspected with the dielectric film 6 interposed between the probe card 1 and the needle tip parts 13, during an inspection of the object to be inspected.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 7, 2020
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Yoshiyuki Fukami, Hidehiro Kiyofuji, Noboru Otabe
  • Publication number: 20200064374
    Abstract: To reduce inspection time by changing an action speed of a movable axis movable part while considering size information of an electrode terminal as a contact destination of a probe. An inspection apparatus of the present disclosure is an inspection apparatus with a plurality of movable probes that brings each of the movable probes into contact with each of a plurality of objects to be inspected on a board to be inspected so as to measure electrical characteristics between the objects to be inspected.
    Type: Application
    Filed: July 18, 2019
    Publication date: February 27, 2020
    Inventor: YOSHIYUKI FUKAMI
  • Publication number: 20190154730
    Abstract: Provided is a probe card with which the adjustment of height deviations of needle tip parts of probes and the adjustment of parallelism between the probes and an object to be inspected are simplified. The probe card 1 has: a wiring substrate 2 having wiring 4 therein or on a surface thereof or the like; a plurality of probes 3; and a dielectric film 6. The dielectric film 6 is disposed to be spaced a distance away from a main surface 8 of the wiring substrate 2 at a position spaced away further from the wiring substrate 2 than the needle tip parts 13 of the probes 3, so that one surface 21 of the dielectric film 6 faces the needle tip parts 13 and faces the main surface 8 that is a probe installation surface of the wiring substrate 2. The probe card 1 configures a state in which the needle tip parts 13 face an electrode of an object to be inspected with the dielectric film 6 interposed between the probe card 1 and the needle tip parts 13, during an inspection of the object to be inspected.
    Type: Application
    Filed: March 21, 2017
    Publication date: May 23, 2019
    Inventors: Yoshiyuki FUKAMI, Hidehiro KIYOFUJI, Noboru OTABE
  • Patent number: 10295590
    Abstract: A probe card having uniform temperature distribution under control to a desired temperature is provided, so as to provide an inspection apparatus and an inspection method. The probe card includes a supporting substrate, a wiring layer arranged including a wiring on a main surface of the supporting substrate, a probe arranged on a surface serving as an opposite side to a side of the supporting substrate of the wiring layer so as to be connected to the wiring, and a plurality of heaters. Further, the probe card is virtually divided into heater regions according to a plurality of heater regions arrayed in vertical and horizontal directions in plan view, and at least one of a plurality of heaters is arranged in each of the plurality of heater regions. An inspection apparatus is configured including the probe card, and an object to be inspected is inspected by use of the inspection apparatus.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 21, 2019
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yuki Saito, Yoshiyuki Fukami, Hidehiro Kiyofuji
  • Publication number: 20170363680
    Abstract: A probe card having uniform temperature distribution under control to a desired temperature is provided, so as to provide an inspection apparatus and an inspection method. The probe card includes a supporting substrate, a wiring layer arranged including a wiring on a main surface of the supporting substrate, a probe arranged on a surface serving as an opposite side to a side of the supporting substrate of the wiring layer so as to be connected to the wiring, and a plurality of heaters. Further, the probe card is virtually divided into heater regions according to a plurality of heater regions arrayed in vertical and horizontal directions in plan view, and at least one of a plurality of heaters is arranged in each of the plurality of heater regions. An inspection apparatus is configured including the probe card, and an object to be inspected is inspected by use of the inspection apparatus.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Yuki SAITO, Yoshiyuki FUKAMI, Hidehiro KIYOFUJI
  • Patent number: 9535108
    Abstract: An inspection apparatus for inspecting an inspection object. The inspection object includes a base body and wiring passing through the base body. The inspection apparatus includes an insulating substrate, a first electrode in the substrate with a portion of the first electrode exposed from a surface of the substrate to form a connection portion which may be electrically connected with the wiring, and a second electrode in the substrate. The first electrode and the second electrode are spaced apart, have mutually parallel portions, and are electrically insulated from each other.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: January 3, 2017
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventor: Yoshiyuki Fukami
  • Patent number: 9476934
    Abstract: An inspection apparatus for inspecting a wiring board having an opposing electrode facing an upper face of the wiring board, a capacitance meter electrically connected to the opposing electrode and the multi-layer wiring, and measuring capacitance between the opposing electrode and the multi-layer wiring, ground, a switch box that is connected to the ground wirings, the opposing electrode, and the ground, and switches to select between a first connection state, in which all the ground wirings are electrically connected to the opposing electrode, and a second connection state, in which one ground wiring is electrically connected to the ground. A control unit extracts a capacitance value by calculating difference between a first capacitance and a second capacitance, wherein capacitance in units of layers of the multi-layer wiring are measured based on the capacitance value extracted by the control unit.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: October 25, 2016
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventor: Yoshiyuki Fukami
  • Patent number: 9095071
    Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 28, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yoshiyuki Fukami, Toshinori Omori, Katsushi Mikuni, Noriko Kon
  • Publication number: 20150108997
    Abstract: An inspection apparatus for inspecting an inspection object. The inspection object includes a base body and wiring passing through the base body. The inspection apparatus includes an insulating substrate, a first electrode in the substrate with a portion of the first electrode exposed from a surface of the substrate to form a connection portion which may be electrically connected with the wiring, and a second electrode in the substrate. The first electrode and the second electrode are spaced apart, have mutually parallel portions, and are electrically insulated from each other.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 23, 2015
    Inventor: Yoshiyuki Fukami
  • Publication number: 20140375351
    Abstract: An inspection apparatus for inspecting a wiring board having an opposing electrode facing an upper face of the wiring board, a capacitance meter electrically connected to the opposing electrode and the multi-layer wiring, and measuring capacitance between the opposing electrode and the multi-layer wiring, ground, a switch box that is connected to the ground wirings, the opposing electrode, and the ground, and switches to select between a first connection state, in which all the ground wirings are electrically connected to the opposing electrode, and a second connection state, in which one ground wiring is electrically connected to the ground. A control unit extracts a capacitance value by calculating difference between a first capacitance and a second capacitance, wherein capacitance in units of layers of the multi-layer wiring are measured based on the capacitance value extracted by the control unit.
    Type: Application
    Filed: April 25, 2014
    Publication date: December 25, 2014
    Applicant: Kabushiki Kaisha Nihon Micronics
    Inventor: Yoshiyuki Fukami
  • Publication number: 20140138139
    Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 22, 2014
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yoshiyuki FUKAMI, Toshinori OMORI, Katsushi MIKUNI, Noriko KON
  • Patent number: 7960988
    Abstract: An electrical test contactor comprises a contactor main body including a plate-shaped attachment portion extending in the up-down direction, a plate-shaped arm portion extending from the lower end portion of the attachment portion at least to one side in the right-left direction, and a plate-shaped pedestal portion projecting downward from the tip end portion of the arm portion, a contact portion projecting downward from the lower end of the pedestal portion and having the lower end of the contact portion acting as a probe tip, and a resistor having a higher resistance value than the contactor main body and the contact portion and arranged at the contactor main body so as to heighten the resistance value of the contactor.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 14, 2011
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Yoshiyuki Fukami, Kazuya Numajiri, Osamu Arai, Hideki Hirakawa
  • Patent number: 7800384
    Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: September 21, 2010
    Assignee: Micronics Japan Co., Ltd.
    Inventor: Yoshiyuki Fukami
  • Patent number: 7659727
    Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: February 9, 2010
    Assignee: Micronics Japan Co., Ltd.
    Inventor: Yoshiyuki Fukami